Single poly cmos imager

Abstract

More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a substrate; and   at least two non-overlapping gate structures formed in a single layer on said substrate, said gate structures being spaced apart by a gap with a dimension y that is less than a dimension x that is lithographically delineated, wherein at least one of the gate structures is a transistor gate structure.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein said gap dimension y measures no less than approximately 1300 Angstroms. 
     
     
         4 . The semiconductor device according to  claim 2 , wherein said gap dimension y measures no less than approximately 1300 Angstroms. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the at least two gate structures are formed of a conductive material selected from polysilicon, silicide, metal, polysilicon and silicide, and polysilicon and metal. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the gate structures are transistor gates in a CCD imager. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the gate structures are transistor gates in a CMOS imager. 
     
     
         8 . The semiconductor device according to  claim 7 , wherein the CMOS imager has one of a 3T, 4T, 5T, 6T or 7T architecture. 
     
     
         9 . The semiconductor device according to  claim 7 , wherein the transistor gates include at least two of a transfer gate, a reset gate, a source follower gate, a row select gate, and a storage gate. 
     
     
         10 . The semiconductor device according to  claim 2 , further comprising a lightly doped region between two adjacent ones of the gate structures. 
     
     
         11 . The semiconductor device according to  claim 10 , wherein the lightly doped region is implanted with ions in the range of about 3·10 11  ions/cm 2  to about 1·10 14  ions/cm 2 . 
     
     
         12 . The semiconductor device according to  claim 11 , wherein the lightly doped region is implanted with ions in the range of about 1·10 12  ions/cm 2  to about 1·10 13  ions/cm 2 . 
     
     
         13 . The semiconductor device according to  claim 10 , wherein the at least two gate structures are transistor gates for a CCD imager. 
     
     
         14 . The semiconductor device according to  claim 10 , wherein the at least two gate structures are transistor gates for a CMOS imager and the two adjacent gate structures having the lightly doped region therebetween are selected from among a transfer gate, a reset gate, a source follower gate, a row select gate and a storage gate. 
     
     
         15 . The semiconductor device according to  claim 14 , wherein the two adjacent gate structures having the lightly doped region therebetween include a transfer gate or a storage gate. 
     
     
         16 . The semiconductor device according to  claim 14 , wherein the two adjacent gate structures having the lightly doped region therebetween are n-channel gates and the lightly doped region therebetween is an n-type region. 
     
     
         17 . The semiconductor device according to  claim 14 , wherein the two adjacent gate structures having the lightly doped region therebetween are p-channel gates and the lightly doped region therebetween is a p-type region. 
     
     
         18 . A semiconductor device comprising:
 a substrate;   a plurality of non-overlapping conductive gates formed over the substrate; and   a lightly doped region in the substrate between two adjacent ones of the plurality of conductive gates, the two adjacent ones of the plurality of conductive gates being formed in a single layer and separated by a gap with a dimension y that is less than a dimension x that is lithographically delineated, wherein at least one of the two adjacent ones of the plurality of gates is a transistor gate.   
     
     
         19 . The semiconductor device according to  claim 18 , wherein the lightly doped region is implanted with ions in the range of about 3·10 11  ions/cm 2  to about 1·10 14  ions/cm 2 . 
     
     
         20 . The semiconductor device according to  claim 19 , wherein the lightly doped region is implanted with ions in the range of about 1·10 12  ions/cm 2  to about 1·10 13  ions/cm 2 . 
     
     
         21 . The semiconductor device according to  claim 20 , wherein the plurality of conductive gates includes transistor gates for a CCD imager. 
     
     
         22 . The semiconductor device according to  claim 18 , wherein the plurality of conductive gates includes transistor gates for a CMOS imager and the two adjacent conductive gates having the lightly doped region therebetween are selected from among a photogate, a transfer gate, a reset gate, a source follower gate, a row select gate and a storage gate. 
     
     
         23 . The semiconductor device according to  claim 22 , wherein the two adjacent conductive gates having the lightly doped region therebetween include a photogate and either a transfer gate or a storage gate. 
     
     
         24 . The semiconductor device according to  claim 22 , wherein the two adjacent conductive gates having the lightly doped region therebetween are n-channel gates and the lightly doped region is an n-type region. 
     
     
         25 . The semiconductor device according to  claim 22 , wherein the two adjacent conductive gates having the lightly doped region therebetween are p-channel gates and the lightly doped region is a p-type region. 
     
     
         26 . The semiconductor device according to  claim 25 , wherein said gap dimension y measures no less than approximately 1300 Angstroms. 
     
     
         27 . The semiconductor device according to  claim 25 , wherein said gap dimension y measures no less than approximately 1300 Angstroms. 
     
     
         28 . An image processing apparatus comprising:
 an image sensor for detecting an image and outputting image signals corresponding to the detected image; and   an image processor for processing the image signals outputted from the image sensor, wherein the image sensor comprises:   a substrate; and   at least two non-overlapping gate structures formed in a single layer on said substrate, said gate structures being spaced apart by a gap with a dimension y that is less than a dimension x that is lithographically delineated, wherein at least one of the gates structures is a transistor gate.   
     
     
         29 . The semiconductor device according to  claim 28 , said gap dimension y measuring no less than approximately 1300 Angstroms. 
     
     
         30 . The image processing apparatus according to  claim 28 , said gap dimension y measuring no less than approximately 300 Angstroms. 
     
     
         31 . The image processing apparatus according to  claim 28 , wherein the image sensor is a CCD image sensor. 
     
     
         32 . The image processing apparatus according to  claim 28 , wherein the image sensor is a CMOS image sensor. 
     
     
         33 . The image processing apparatus according to  claim 28 , further comprising a lightly doped region between two of the gate structures. 
     
     
         34 . An image processing apparatus comprising:
 an image sensor for detecting an image and outputting image signals corresponding to the detected image; and   an image processor for processing the image signals outputted from the image sensor, wherein the image sensor comprises:   a substrate;   a plurality of conductive gates formed over the substrate; and a lightly doped region in the substrate between at least one pair of adjacent non-overlapping conductive gates formed in a single layer and separated by a gap with a dimension y that is less than a dimension x that is lithographically delineated.   
     
     
         35 . A processing system, comprising:
 a processor for receiving and processing image data; and   an image data generator for supplying image data to the processor, the image data generator comprising an image sensor for obtaining an image and outputting an image signal, an image processor for processing the image signal, and a controller for controlling the image sensor and the image processor, wherein the image sensor comprises:   a substrate, and at least two non-overlapping gate structures formed in a single layer on said substrate, said gate structures being spaced apart by a gap with a dimension y that is less than a dimension x that is lithographically, wherein at least one of the gate structures is a transistor gate.   
     
     
         36 . The processing system according to  claim 35 , wherein the image sensor is a CCD imager. 
     
     
         37 . The processing system according to  claim 35 , wherein the image sensor is a CMOS imager. 
     
     
         38 . The processing system according to  claim 35 , further comprising a lightly doped region between at least one pair of adjacent gate structures. 
     
     
         39 . A processing system, comprising:
 a processor for receiving and processing image data; and   an image data generator for supplying image data to the processor, the image data generator comprising an image sensor for obtaining an image and outputting an image signal, an image processor for processing the image signal, and a controller for controlling the image sensor and the image processor, wherein the image sensor comprises:   a substrate;   a plurality of non-overlapping conductive gates formed over the substrate; and   a lightly doped region in the substrate between two adjacent ones of the plurality of conductive gates, the adjacent conductive gates being formed in a single layer and separated by a gap with a dimension y that is less than a dimension x that is lithographically.