Non-volatile semiconductor memory device

Abstract

When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.

1 . A memory system comprising a memory device, the memory device further comprising:
 a memory cell array including electrically erasable programmable non-volatile semiconductor memory cells;   a controller configured to control operations of reading, programming and erasing of data in said memory cell array;   a voltage level detector configured to detect if a supply voltage reaches a recovery voltage level;   a signal generator configured to generate a recovery operation instructing signal for instructing a recovery operation that halts operations of reading, programming and erasing and initiates voltages applied at least to said memory cell array when said voltage level detector detects that said supply voltage reaches said recovery voltage level; and   a switching circuit configured to invalidate said recovery operation instructing signal if a user sequence operation mode is executed and to validate said recovery operation instructing signal if a data entry operation mode is executed.   
     
     
         2 . The memory system according to  claim 1 , wherein said switching circuit is configured to receive a recovery operation inhibiting signal for inhibiting execution of said recovery operation, said switching circuit being operative to invalidate said recovery operation instructing signal when said recovery operation inhibiting signal is entered. 
     
     
         3 . The memory system according to  claim 2 , wherein said switching circuit is configured to receive an operation mode specifying signal for specifying an operation mode, said recovery operation inhibiting signal being allowed to enter when an operation mode specifying signal for indicating the data entry operation mode. 
     
     
         4 . The memory system according to  claim 1 , wherein said memory cell array is partly used as an initialization data region for storing initialization data that determines a memory operating condition. 
     
     
         5 . The memory system according to  claim 4 , wherein said initialization data region is not accessible from external during a normal operation. 
     
     
         6 . The memory system according to  claim 4 , wherein said initialization data region is excluded from an erasing condition during erasing said memory cell array. 
     
     
         7 . The memory system according to  claim 4 , further comprising a data latch to store said initialization data read out of said controller. 
     
     
         8 . The memory system according to  claim 4 , wherein said switching circuit is operative to validate said recovery operation instructing signal during execution of reading said initialization data. 
     
     
         9 . The memory system according to  claim 4 , wherein said initialization data contains switching data for switching between validation and invalidation of said recovery operation instructing signal at each operation mode,
 said switching circuit is configured to switch validation/invalidation of said recovery operation instructing signal based on said switching data read out.   
     
     
         10 . The memory system according to  claim 1 , further comprising a power-on reset circuit operative to detect if power is turned on, wherein said controller begins operating after said power-on reset circuit begins operating. 
     
     
         11 . The memory system according to  claim 1 , wherein said memory cell array comprises a NAND cell unit including a plurality of memory cells connected in series. 
     
     
         12 . The non-volatile semiconductor memory device according to  claim 4 , wherein said detector is further configured to detect if said supply voltage elevates to an initialization voltage level higher than said recovery voltage level after power is turned on. 
     
     
         13 . The non-volatile semiconductor memory device according to  claim 12 , wherein said signal generator is configured to generate an initialization data read instructing signal for instructing said controller to read out said initialization data when said voltage level detector detects that said supply voltage reaches said initialization voltage level. 
     
     
         14 . The non-volatile semiconductor memory device according to  claim 13 , wherein said initialization data read instructing signal and said recovery operation instructing signal generated from said signal generator rise when said supply voltage reaches said initialization voltage level and fall when said supply voltage reaches said recovery voltage level. 
     
     
         15 . The non-volatile semiconductor memory device according to  claim 12 , wherein said voltage level detector is configured to detect a plurality of voltage levels as said recovery voltage level,
 said plurality of voltage levels being switched at each operation mode based on said switching data stored in said initialization data.   
     
     
         16 . The non-volatile semiconductor memory device according to  claim 13 , wherein said signal generator is configured to generate a hysteresis signal that rises when said supply voltage reaches said initialization voltage level and falls when said supply voltage reaches said recovery voltage level. 
     
     
         17 . The non-volatile semiconductor memory device according to  claim 16 , wherein said hysteresis signal is invalidated in the user sequence operation mode.