System and a method for constructing and deconstructing data packets

Abstract

A packet processing data path is attached to the processor bus as a slave via a bus interface. The packet processing data path comprises a number of blocks. Respective blocks comprise configuration registers operable to provide information on what operation the blocks should perform for the current packet field being processed. The bus interface comprises a first register operable to control a bus of Update Enable signals, which bus is also connected to the blocks. The bus interface also comprises a second register operable to control a Mode signal, which is also connected to the blocks. An Update Mode signal is connected to the bus interface and to the blocks. A write to the second register causes the Update Mode signal to be pulsed active, triggering the enabled configuration registers to update their values.

1 . An apparatus, comprising:
 a number of processing blocks to storing predefined configuration modes, the predefined configuration modes determining values of different fields of different data packets; and   a mode register to cause a parallel update of the predefined configuration modes in the number of processing blocks in response to a mode signal provided by a bus interface in order to provide a certain field of a data packet.   
     
     
         2 . The apparatus of  claim 1 , wherein the update of the predefined configuration modes may be independently disabled. 
     
     
         3 . The apparatus of  claim 1 , further comprising additional registers to store predefined configuration mode settings for respective processing block. 
     
     
         4 . The apparatus of  claim 1 , further comprising hardwired predefined configuration mode settings for respective processing blocks. 
     
     
         5 . The processing data path of  claim 1 , further comprising a set of registers operable to disable and/or enable the update of the predefined configuration modes in the processing blocks. 
     
     
         6 . A system, comprising:
 a processing data path comprising processing blocks, respective processing blocks comprising configuration registers to store information on an operation to be performed by the processing blocks for a current packet being processed; and   a bus interface including a first register for controlling a bus of Update Enable signals being receivable by the number of processing blocks, and a second register for controlling a Mode signal being receivable by the processing blocks, the bus interface providing an Update Mode signal to the number of processing blocks, wherein a write to the second register causes the Update Mode signal to be pulsed, thereby triggering enabled configuration registers to update their values.   
     
     
         7 . The system of  claim 6 , further comprising a processor operatively coupled to a processor bus, the packet processing data path being operatively coupled to the processor, and the packet processing data path being operatively coupled to the processor bus as a slave via a bus interface, the system being operable to support a number of different coding formats. 
     
     
         8 . The system of  claim 6 , wherein the bus interface is operable to decode a bus protocol and perform write and/or read operations to the configuration registers. 
     
     
         9 . The system of  claim 6 , further comprising additional registers operable to store pre-defined modes for respective configuration registers, wherein complete mode definitions, for respective configuration registers comprise whether the configuration registers should be updated, and if so what values the registers it should be set to. 
     
     
         10 . The system of  claim 6 , wherein pre-defined modes for respective configuration registers are hardwired, and wherein complete mode definitions, for respective configuration registers, comprise whether the configuration registers should be updated, and if so what values the registers should be set to. 
     
     
         11 . A method, comprising:
 transmitting a write signal to a register which then transmits a Mode signal to processing blocks;   transmitting Update Enable signals to configuration registers to be updated for new mode;   pulsing an Update Mode signal active; and   transmitting the active Update Mode signal to processing blocks thereby triggering enabled configuration registers to update their values in parallel.   
     
     
         12 . The method of  claim 11 , further comprising enabling or disabling the update of the configuration registers with the aid of a set of registers. 
     
     
         13 . The method of  claim 11 , further comprising storing pre-defined modes for respective configuration registers, wherein complete mode definitions, for respective configuration registers, comprise whether the configuration registers should be updated, and if so what values the registers should be set to. 
     
     
         14 . The method of  claim 11 , further comprising hardwiring pre-defined modes for respective configuration registers, wherein complete mode definitions, for respective configuration registers, comprise whether the configuration registers should be updated, and if so what values the registers should be set to. 
     
     
         15 . The method of  claim 11 , further comprising storing a pre-defined mode for some of the configuration registers; and hardwiring a predefined mode for other of the configuration registers, wherein complete mode definitions, for respective configuration registers, comprise whether the configuration registers should be updated, and if so what value the registers should be set to.