Encryption processor of memory card and method for writing and reading data using the same

Abstract

An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

1 . An encryption processor of a memory card for storing encrypted data in a memory chip, the encryption processor comprising:
 a first-in, first-out (FIFO) memory for sequentially outputting m-bit data (m being a positive integer) in response to a first control signal;   an encryption key generator for generating m-bit encrypted XOR keys in response to a second control signal and for sequentially outputting the encrypted XOR keys in response to a third control signal;   a logic operator for performing an XOR operation on the data output from the FIFO memory and the encrypted XOR keys output from the encryption key generator during a data write operation to sequentially encrypt the data to obtain m-bit encrypted data, the encrypted data being sent to a memory interface; and   a control circuit for generating the first control signal, the second control signal and the third control signal in response to a write command and a write address during the data write operation, the first control signal being provided to the FIFO memory, and the second and third control signals being provided to the encryption key generator.