Semiconductor device and method of fabricating the same

Abstract

A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.

1 . A semiconductor device, comprising:
 a gate electrode disposed over a substrate;   a plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope;   a capping layer disposed between the gate electrode and the plug; and   a gate hard mask layer whose sidewall disposed over the gate electrode extending to a top surface of the capping layer.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a recess pattern formed in the substrate under the gate electrode. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the recess pattern has one shape selected from the group consisting of rectangle, polygon, a bulb type, a fin type and a saddle-fin type. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a sidewall of the gate electrode has a vertical profile or a positive slope. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a sidewall of the capping layer has a negative slope. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the capping layer includes one of an oxide layer, a nitride layer, an oxynitride layer, and a stack structure thereof. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the plug is formed of the same material as that of the gate electrode. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the gate electrode comprises a first gate electrode and a second gate electrode that are sequentially stacked. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the plug is formed of the same material as that of the first gate electrode. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the plug includes a silicon layer. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the second gate electrode includes a metallic layer. 
     
     
         12 . The semiconductor device of  claim 9 , wherein the gate electrode further comprises a barrier metal layer disposed between the first gate electrode and the second gate electrode. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the barrier metal layer extends to a region between the second gate electrode and the capping layer.