Method for Planarization of Wafer and Method for Formation of Isolation Structure in Top Metal Layer

Abstract

The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

1 . A method for planarization of a wafer having a surface layer with a recess, comprising:
 forming an etching-resist layer over the surface layer, a thickness of the etching-resist layer in the recess being larger than that outside the recess;   etching the etching-resist layer and the surface layer; wherein, an etching speed of the surface layer is higher than that of the etching-resist layer, so that the surface layer outside the recess will not be higher than the bottom of recess;   removing the etching-resist layer in the recess.   
     
     
         2 . The method according to  claim 1 , wherein the etching-resist layer is a PR (photoresist) layer. 
     
     
         3 . The method according to  claim 2 , wherein the method further comprises a process of patterning the etching-resist layer after the etching-resist layer is formed on the surface layer and before the etching-resist layer and the surface layer are etched, so as to remove the etching-resist layer outside the recess. 
     
     
         4 . The method according to  claim 1 , wherein the etching-resist layer is a BARC (Bottom Anti-Reflection Coat) layer. 
     
     
         5 . The method according to  claim 1 , wherein the etching-resist layer is formed by a spin-coating process. 
     
     
         6 . The method according to  claim 1 , wherein the surface layer is made of one selected from a group consisting of silicon oxide, silicon nitride and aluminum (Al). 
     
     
         7 . The method according to  claims 6 , wherein the etching-resist layer and the surface layer are etched by a dry etching process. 
     
     
         8 . The method according to  claim 6 , wherein a main etching gas for etching the etching-resist layer and the surface layer comprises at least one of CxFy and CHxFy, wherein 1≦X≦9, 1≦Y≦9, in the case that the surface layer is a silicon oxide or a silicon nitride layer. 
     
     
         9 . The method according to  claims 6 , wherein the etching gas for etching the etching-resist layer and the surface layer comprises an etching gas containing halogen family elements, in the case that the surface layer is an Al layer. 
     
     
         10 . The method according to  claim 1 , wherein the etching-resist layer is removed by an ashing process.