Recess gate transistor

Abstract

A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

1 . A semiconductor device, comprising:
 a substrate having a plurality of trenches, each of the trenches disposed between contacts formed on the top surface of an ILD layer formed on the substrate, each trench having trench walls and extending vertically from a bottom portion to an upper portion;   an insulating layer formed on the trenches including the bottom portions and the trench walls;   a conductive layer pattern formed at the bottom portion of each of the trenches;   a buffer layer formed on the conductive layer pattern and the trench walls; and   a cap formed on the buffer layer from above the conductive layer patterns to the top of the trenches.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the distance from trench-to-trench is 0.1 um or less. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the substrate is partitioned into a cell region, a core region, and a peripheral region, wherein the trenches are disposed in the cell region and not in the core region or the peripheral region. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the buffer layer is made of silicon oxide, and the cap is made of silicon nitride. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the ILD layer is made of BPSG. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the cap comprises more than one capping layer. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the conductive layer pattern comprises a first conductive layer and a second conductive layer made of different conductive materials. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the first conductive layer is made from a metal group consisting of one of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru, and the second conductive layer is made from polysilicon, 
     
     
         9 . A semiconductor memory card, comprising:
 a memory controller and a memory device, the memory controller controls the memory device to read or write data from/into the memory in response to a read/write request of a host, wherein the memory device comprises: a substrate having a plurality of trenches, each of the trenches disposed between contacts formed on the top surface of an ILD layer formed on the substrate, each trench having trench walls and extending vertically from a bottom portion to an upper portion; an insulating layer formed on the trenches including the bottom portions and the trench walls; a conductive layer pattern formed at the bottom portion of each of the trenches; a buffer layer formed on the conductive layer pattern and the trench walls; and a cap formed on the buffer layer from above the conductive layer patterns to the top of the trenches.   
     
     
         10 . The semiconductor memory card of  claim 9 , wherein the distance from trench-to-trench of the memory device is 0.1 um or less. 
     
     
         11 . The semiconductor memory card of  claim 9 , wherein the host is a mobile device or a processing device having a processor. 
     
     
         12 . The semiconductor memory card of  claim 9 , further including a wireless interface for communicating with another cellular device. 
     
     
         13 . The semiconductor memory card of  claim 9 , further including a connector for removably connecting to a host system, wherein the host system is one of a personal computer, notebook computer, hand held computing device, camera, or audio reproducing device. 
     
     
         14 . An electronic device comprising:
 a controller having a processor; an input/output (I/O) device; a memory device; and a wireless interface, wherein the I/O device includes a display, wherein the wireless interface transmits or receives data via a wireless communication network, and wherein the memory device comprises: a substrate having a plurality of trenches, each of the trenches disposed between contacts formed on the top surface of an ILD layer formed on the substrate, each trench having trench walls and extending vertically from a bottom portion to an upper portion; an insulating layer formed on the trenches including the bottom portions and the trench walls; a conductive layer pattern formed at the bottom portion of each of the trenches; a buffer layer formed on the conductive layer pattern and the trench walls; and a cap formed on the buffer layer from above the conductive layer patterns to the top of the trenches.   
     
     
         15 . The electronic device of  claim 14 , wherein the wireless communication network communicates in a communication interface protocol of a third generation communication system, including one of code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended-time division multiple access (E-TDMA), wide band code division multiple access (WCDMA), or CDMA2000.