US2012011480A1PendingUtilityA1

Logic-Driven Layout Verification

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Assignee: SRINIVASAN SRIDHARPriority: May 25, 2010Filed: Nov 22, 2010Published: Jan 12, 2012
Est. expiryMay 25, 2030(~3.9 yrs left)· nominal 20-yr term from priority
A61K 38/4846A61K 47/02A61K 39/395A61K 38/00G06F 2119/18G06F 30/398G06F 30/39
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Claims

Abstract

A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.

Claims

exact text as granted — not AI-modified
1 - 8 . (canceled) 
     
     
         9 . A method of logic-driven layout verification, comprising:
 receiving one or more schematic logic features and a rule file;   translating the one or more schematic logic features to layout features;   identifying one or more layout structures corresponding to the layout features;   applying a design rule checking (DRC) or design for manufacturability (DFM) check to the one or more layout structures according to the rule file; and   storing or reporting the result of DRC or DFM check.

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