Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region.

1 . A semiconductor device comprising:
 a semiconductor substrate including a cell region and a peripheral region;   a mask pattern formed over the semiconductor substrate;   a bit line contact hole extending through the mask pattern to expose the semiconductor substrate in the cell region;   a bit line contact plug formed within the bit line contact hole and electrically coupling the semiconductor substrate; and   a bit line formed over the bit line contact plug, the bit line and the bit line contact plug having substantially the same width.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the mask pattern is a gate mask pattern used to define the recess, the gate mask pattern including oxide or nitride, or both. 
     
     
         3 . The semiconductor device according to  claim 1 , further comprising a spacer provided at sidewalls of the bit line contact hole, the spacer including oxide, nitride, or both. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the mask pattern has a thickness ranging from 50 Å to 100 Å. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the bit line includes:
 a barrier metal layer formed over the bit line contact plug;   a bit line conductive layer formed over the barrier metal layer;   a hard mask layer formed over the bit line conductive layer; and   a spacer formed at sidewalls of a stack structure including the barrier metal layer, the bit line conductive layer and the hard mask layer.   
     
     
         6 . The semiconductor device according to  claim 5 , further comprising a peri-gate pattern formed over the semiconductor substrate in the peripheral region,
 wherein the peri-gate pattern in the peripheral region has the substantially same structure as that of the bit line formed in the cell region.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the bit line conductive layer defining the bit line in the cell region has a less thickness than a conductive layer defining the peri-gate pattern in the peripheral region. 
     
     
         8 . The semiconductor device according to  claim 1 , further comprising a buried-type gate buried in the cell region of the semiconductor substrate. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein the buried gate pattern comprises:
 a gate oxide film formed over the inner surface of the recess;   a gate electrode formed over the gate oxide film and within recess at a lower portion of the recess; and   a capping film formed over the gate electrode and filling the recess.   
     
     
         10 . A method for manufacturing a semiconductor device, the method comprising:
 providing a semiconductor substrate including a cell region and a peripheral region;   forming a mask pattern over the semiconductor substrate in the cell region;   etching the mask pattern to form a bit line contact hole exposing the semiconductor substrate;   forming a conductive pattern within the bit line contact hole;   forming a conductive layer over the conductive pattern; and   etching the conductive layer and the conductive pattern to define a bit line and a bit line contact plug having substantially the same width.   
     
     
         11 . The method according to  claim 10 , further comprising forming a first polysilicon layer over the mask pattern in the cell region and over the semiconductor substrate in the peripheral region. 
     
     
         12 . The method according to  claim 11 , wherein the conductive pattern is formed by etching the first polysilicon layer disposed over the mask pattern in the cell region. 
     
     
         13 . The method according to  claim 10 , further comprising forming a spacer on a side wall of the bit line contact hole, the spacer including any of an oxide film, a nitride film and a stack structure including an oxide film and a nitride film at sidewalls of the bit line contact hole. 
     
     
         14 . The method according to  claim 10 , further comprising:
 forming a second polysilicon layer over the cell region and the peripheral region; and   removing a given thickness of the second polysilicon layer in the cell region.   
     
     
         15 . The method according to  claim 10 , wherein the mask pattern includes oxide or nitride, or both. 
     
     
         16 . The method according to  claim 10 , wherein the mask pattern is formed to have a thickness ranging from 50 Å to 100 Å. 
     
     
         17 . The method according to  claim 10 , wherein bit line includes a barrier metal layer formed over the bit line contact plug, a bit line conductive layer formed over the barrier metal layer, and a hard mask layer formed over the bit line conductive layer. 
     
     
         18 . The method according to  claim 17 , the method further comprising:
 forming a storage node contact hole that exposes the semiconductor substrate in the cell region; and   is etching the mask pattern disposed at a side of the storage node contact hole to enlarge the bottom width of the storage node contact hole.   
     
     
         19 . The method according to  claim 10 , further comprising forming a gate in the peripheral region, wherein the gate in the peripheral region is formed simultaneously with the bit line in the cell region. 
     
     
         20 . The method according to  claim 10 , wherein the conductive pattern is a polysilicon pattern. 
     
     
         21 . A semiconductor device comprising:
 a substrate including a cell region and a peripheral region;   a buried cell gate pattern formed in the substrate in the cell region;   a gate mask pattern formed over the substrate in the cell region, the gate mask pattern defining the buried cell gate pattern;   a bit line contact plug formed through the mask pattern electrically coupling a first side of the buried cell gate pattern; and   a storage node contact plug formed through the mask pattern electrically coupling a second side of the buried cell gate pattern,   wherein a top level of the bit line contact plug is no higher than a top level of the gate mask pattern in the cell region.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein the thickness of the gate mask pattern is in a range from 50 Å to 100 Å. 
     
     
         23 . The semiconductor device according to  claim 21 , wherein the bit line contact plug extends into the substrate, the substrate being a semiconductor substrate. 
     
     
         24 . The semiconductor device according to  claim 21 , further comprising an upper bit line pattern formed over the bit line contact plug,
 wherein the bit line contact plug and the upper bit line pattern are formed in a single process step to form a vertically uniform profile with substantially no step difference.   
     
     
         25 . The semiconductor device according to  claim 24 , further comprising a peri-gate pattern formed over the substrate in the peripheral region,
 wherein the peri-gate pattern is formed simultaneously with the upper bit line pattern and the bit line contact plug by employing a Gate-Bit-Line (GBL) process.