Nonvolatile flash memory structures including fullerene molecules and methods for manufacturing the same

Abstract

Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C 60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C 60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application. Embodiments also contemplate engineered fullerene molecules incorporated within the context of at least one of a tunneling dielectric and a floating gate within a nonvolatile flash memory structure.

1 . A semiconductor device comprising:
 a semiconductor substrate; and   a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell comprising:
 a tunnel insulating film provided over a surface of the semiconductor substrate, the tunnel insulating film comprising a layer of monodispersed molecules; 
 a charge storage layer provided on the tunnel insulating film; 
 an insulating film provided on the charge storage layer; and 
 a conductive layer provided on the insulating film. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein said monodispersed molecules include fullerene molecules. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the fullerene molecules comprise C 60  molecules. 
     
     
         4 . The semiconductor device of  claim 3 , wherein C 60  molecules include variable prescribed energy level characteristics by chemical functionalization. 
     
     
         5 . The semiconductor device of  claim 1 , wherein said monodispersed molecules are conductive, and wherein the monodispersed molecules comprise C 60  molecules and a metal molecule, wherein the metal molecule comprises chromium or titanium. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the layer of monodispersed molecules are between first and second tunnel insulating layers. 
     
     
         7 . The semiconductor device according to  claim 6 , wherein the first and second tunnel insulating layers or the insulating film comprise a silicon oxide film or a dielectric insulating film. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the layer of monodispersed molecules is about 0.5 nm thick, less than 1 nm thick, less than 1.2 nm thick, less than 2 nm thick, or less than 3 nm thick, and wherein the first and second tunnel insulating layers are less than 8 nm thick, less than 5 nm thick, less than 3 nm thick, less than 2 nm thick, or less than 1 nm thick. 
     
     
         9 . The semiconductor device of  claim 1  comprising:
 a first electrode coupled to a first impurity region in the semiconductor substrate; 
 a second impurity region in the semiconductor substrate; and 
 an electrode coupled to a channel region in the semiconductor substrate between the first impurity region and the second impurity region, wherein the tunnel insulating film is over a portion of the channel region. 
 
     
     
         10 . The semiconductor device according to  claim 9 , wherein the conductive layer is a control electrode, the first electrode is a source electrode and the second electrode is a drain electrode, wherein the first and second impurity regions comprise an n-type impurity or a p-type impurity. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the nonvolatile memory cell stores more than one bit of data. 
     
     
         12 . The semiconductor device according to  claim 1 , wherein the semiconductor device comprises an array of memory cells, wherein the nonvolatile memory cell is a NAND type nonvolatile memory cell, or a NOR type nonvolatile memory cell. 
     
     
         13 . The semiconductor device of  claim 1 , wherein the semiconductor device comprises a flash memory card, an EEPROM device, or a nonvolatile memory device. 
     
     
         14 . A nonvolatile flash memory card, comprising:
 a random access memory array;   an input/output unit to operatively connect the random access memory to receive or transmit data; and   a microcontroller to control data storage or data retrieval between the input/output unit and the random access memory array, wherein at least one cell of the random access memory array comprises,
 a semiconductor region having a source region, a drain region, and a channel region provided between the source region and the drain region, 
 a first tunnel insulation film formed on the channel region, 
 a barrier layer formed on the first tunnel insulation film, the barrier layer comprising a layer of monodispersed molecules, the barrier layer including a prescribed energy barrier level, 
 a second tunnel insulation film formed on the barrier layer, 
 a charge storage portion formed over the second tunnel insulation film, and 
 a control electrode on the charge storage portion. 
   
     
     
         15 . The nonvolatile flash memory card of  claim 14 , wherein said barrier layer is monodispersed molecules are-fullerene molecules. 
     
     
         16 . The nonvolatile flash memory card of  claim 15 , wherein the fullerene molecules comprise C 60  molecules. 
     
     
         17 . The nonvolatile flash memory card of  claim 14 , wherein said monodispersed molecules are conductive. 
     
     
         18 . A method of forming a tunnel barrier for a semiconductor device, comprising:
 providing an active region at a semiconductor substrate; and   providing a tunnel insulating film over the active region, wherein providing the tunnel insulating film comprises,
 forming a first tunnel insulation layer formed over the active region, 
 forming a layer of conductive fullerene molecules over the first tunnel insulation layer, and 
 forming a second tunnel insulation layer formed over the monodispersed fullerene molecules, wherein the tunnel insulating film comprises the tunnel barrier. 
   
     
     
         19 . The method of forming a tunnel barrier for a semiconductor device of  claim 18 , comprising:
 providing a charge storage layer over the tunnel insulating film;   providing an insulating film provided on the charge storage layer; and   providing a conductive layer provided on the insulating film.   
     
     
         20 . A semiconductor structure comprising:
 a semiconductor substrate including a source region and a drain region that are separated by a channel region;   a tunneling dielectric located over the channel region;   a floating gate located over the tunneling dielectric;   a blocking dielectric located over the floating gate; and   a control gate located over the blocking dielectric, where at least one of the tunneling dielectric and the floating gate comprises at least in-part an engineered fullerene molecule.   
     
     
         21 . The semiconductor structure of  claim 20  wherein the semiconductor substrate comprises a silicon semiconductor substrate. 
     
     
         22 . The semiconductor structure of  claim 20  wherein the engineered fullerene molecule is included within the tunneling dielectric. 
     
     
         23 . The semiconductor structure of  claim 20  wherein the engineered fullerene molecule is included within the floating gate. 
     
     
         24 . The semiconductor structure of  claim 20  wherein the engineered fullerene molecule is included within both the tunneling dielectric and the floating gate. 
     
     
         25 . The semiconductor structure of  claim 20  wherein the engineered fullerene molecule has the chemical formula C n R m , wherein:
 n is selected from the group consisting of 60, 70, 76, 78, 84; and 
 m is an integer between 1 and 48. 
 
     
     
         26 . The semiconductor structure of  claim 25  wherein R comprises a pendant moiety selected from the group consisting of hydrogen, halogen, —OH, —CN, aromatic and alkyl group radical pendent moieties. 
     
     
         27 . The semiconductor structure of  claim 26  wherein the pendant moiety is covalently bonded to a base fullerene molecule. 
     
     
         28 . The semiconductor structure of  claim 20  wherein the engineered fullerene molecule is selected to provide a coulomb staircase effect when electrically actuating the semiconductor structure 
     
     
         29 . A method for forming a semiconductor structure comprising:
 forming a tunneling dielectric material layer over a semiconductor substrate;   forming a floating gate material layer over the tunneling dielectric material layer;   forming a blocking dielectric material layer over the floating gate material layer; and   forming a control gate material layer over the blocking dielectric material layer to provide a blanket gate stack layer from the foregoing four material layers where at least one of the tunneling dielectric material layer and the floating gate material layer is formed at least in-part from an engineered fullerene molecule material layer;   patterning at least a portion of the blanket gate stack layer to form a gate stack: and   forming a source region and a drain region separated by a channel region beneath the gate stack into the semiconductor substrate while using the gate stack as a mask.   
     
     
         30 . The method of  claim 29  wherein the engineered fullerene material layer is formed using a spin coating method. 
     
     
         31 . The method of  claim 29  wherein the semiconductor substrate comprises a silicon semiconductor substrate. 
     
     
         32 . The method of  claim 29  wherein the engineered fullerene molecule material layer is included within the tunneling dielectric material layer. 
     
     
         33 . The method of  claim 29  wherein the engineered fullerene molecule material layer is included within the floating gate material layer. 
     
     
         34 . The method of  claim 29  wherein the engineered fullerene molecule material layer is included within both the tunneling dielectric material layer and the floating gate material layer. 
     
     
         35 . The method of  claim 29  wherein the engineered fullerene molecule has the chemical formula C n R m , wherein:
 n is selected from the group consisting of 60, 70, 76, 78, 84; and 
 m is an integer between 1 and 48. 
 
     
     
         36 . The method of  claim 35  wherein R comprises a pendant moiety selected from the group consisting of hydrogen, halogen, —OH, —CN, aromatic and alkyl group radical pendent moieties. 
     
     
         37 . The method of  claim 36  wherein the pendant moiety is covalently bonded to the base fullerene molecule. 
     
     
         38 . The method of  claim 29  wherein the engineered fullerene molecule is selected to provide a coulomb staircase effect when electrically actuating the semiconductor structure