Semiconductor device and semiconductor package including the same

Abstract

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

1 . A semiconductor device, comprising:
 a first chip including at least one decoupling capacitor; and   a second chip stacked over the first chip, including internal circuits.   
     
     
         2 . The semiconductor device of  claim 1 , wherein one end of the decoupling capacitor is connected to a power pad and the end of the decoupling capacitor is connected to a ground pad. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising a connector formed through the second chip, connecting between the first chip and the second chip. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the connector connects between a power pad of the first chip and that of the second chip. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the connector connects between a ground pad of the first chip and that of the second chip. 
     
     
         6 . The semiconductor device of  claim 3 , the connector is a via formed by a Through Silicon Via (TSV) process. 
     
     
         7 . A semiconductor package, comprising:
 a wire board;   a first chip stacked over the wire board, including at least one decoupling capacitor; and   a second chip stacked over the first chip, including internal circuits.   
     
     
         8 . The semiconductor package of  claim 7 , wherein one end of the decoupling capacitor is connected to a power pad and the other end of the decoupling capacitor is connected to a ground pad. 
     
     
         9 . The semiconductor package of  claim 7 , further comprising a first connector formed through the first chip, connecting between the wire board and the first chip. 
     
     
         10 . The semiconductor package of  claim 9 , further comprising a second connector formed through the second chip, connecting between the first chip and the second chip. 
     
     
         11 . The semiconductor package of  claim 10 , wherein the second connector connects a power pad of the first chip and that of the second chip. 
     
     
         12 . The semiconductor package of  claim 10 , wherein the second connector connects between a ground pad of the first chip and that of the second chip. 
     
     
         13 . The semiconductor package of  claim 10 , the second connector is a via formed by a Through Silicon Via (TSV) process. 
     
     
         14 . The semiconductor package of  claim 7 , further comprising an encapsulation body for protecting the first and second chips, respectively.