Driving circuit of light emitting diode, decoding circuit and decoding method thereof

Abstract

A driving circuit, a decoding circuit and a decoding method thereof are provided. The decoding circuit includes an oscillator and a decoder including a frequency determining unit and a decoding unit. The frequency determining unit receives a clock signal and a data signal which is corresponding to DMX512 protocol, and samples one slot of the data signal according to the clock signal to generate a sample number corresponding to a slot period of the slot. Then, the frequency determining unit outputs a reference signal corresponding to the frequency of the clock signal according to the sample number. The decoding unit samples the data signal according to the clock signal and the reference signal to decode data carried on the data signal. The decoding circuit is able to sample the data signal correctly without disposing any external frequency adjusting element.

1 . A decoding circuit for decoding a data signal, comprising:
 an oscillator for outputting a clock signal; and   a decoder, coupled to the oscillator, for receiving the clock signal and the data signal, the data signal including a plurality of slots, each slot having a slot period, wherein the decoder samples one of the slots based on the clock signal to generate a sample number corresponding to the slot period and calculates a frequency of the clock signal according to the sample number, and then decodes data of the data signal according to the frequency of the clock signal.   
     
     
         2 . The decoding circuit according to  claim 1 , wherein the decoder further comprises:
 a frequency determining unit, coupled to the oscillator, for receiving the clock signal and the data signal, wherein the frequency determining unit samples one of the slots based on the clock signal to generate the sample number corresponding to the slot period and outputs a reference signal corresponding to the frequency of the clock signal according to the sample number; and   a decoding unit, coupled to the frequency determining unit and the oscillator, wherein the decoding unit samples the data signal based on the clock signal and the reference signal to decode the data of the data signal.   
     
     
         3 . The decoding circuit according to  claim 1 , wherein a format of the data signal is corresponding to a DMX512 protocol and the frequency determining unit samples a first slot of the slots to generate the sample number. 
     
     
         4 . The decoding circuit according to  claim 3 , wherein the first slot has a start code. 
     
     
         5 . The decoding circuit according to  claim 2 , wherein the frequency determining unit samples at least one bit in the first slot of the slots based on the clock signal to generate the sample number. 
     
     
         6 . The decoding circuit according to  claim 5 , wherein the first slot has a default code. 
     
     
         7 . The decoding circuit according to  claim 2 , wherein the oscillator, the frequency determining unit and the decoding unit are integrated in the same chip. 
     
     
         8 . A driving circuit of light emitting diode (LED), comprising:
 a decoding circuit, comprising:
 an oscillator for outputting a clock signal; and 
 a decoder, coupled to the oscillator, for receiving the clock signal and a data signal, the data signal including a plurality of slots, each slot having a slot period, wherein the decoder samples one of the slots based on the clock signal to generate a sample number corresponding to the slot period of the slot and calculates a frequency of the clock signal according to the sample number, and then decodes data of the data signal according to the frequency of the clock signal; and 
   a driving unit, coupled to the decoding circuit, for outputting an LED drive signal according to the data of the data signal.   
     
     
         9 . The driving circuit of LED according to  claim 8 , wherein the decoder comprises:
 a frequency determining unit, coupled to the oscillator, for receiving the clock signal and the data signal, wherein the frequency determining unit samples one of the slots based on the clock signal to generate the sample number corresponding to the slot period of the slot and outputs a reference signal corresponding to the frequency of the clock signal according to the sample number; and   a decoding unit, coupled to the frequency determining unit and the oscillator, wherein the decoding unit samples the data signal based on the clock signal and the reference signal to decode the data of the data signal.   
     
     
         10 . The driving circuit of LED according to  claim 8 , wherein the format of the data signal corresponds to the DMX512 protocol and the frequency determining unit samples a first slot of the slots to generate the sample number. 
     
     
         11 . The driving circuit of LED according to  claim 10 , wherein the first slot has a start code. 
     
     
         12 . The driving circuit of LED according to  claim 9 , wherein the frequency determining unit samples at least one bit in the first slot of the slots based on the clock signal to generate the sample number. 
     
     
         13 . The driving circuit of LED according to  claim 12 , wherein the first slot has a default code. 
     
     
         14 . The driving circuit of LED according to  claim 9 , wherein the oscillator, the frequency determining unit, the decoding unit and the driving unit are integrated into the same chip. 
     
     
         15 . A decoding method suitable for decoding a data signal corresponding to a DMX512 protocol, the decoding method comprising:
 receiving a clock signal and a data signal, wherein the data signal has a plurality of slots and each slot has a slot period;   sampling one of the slots based on the clock signal to generate a sample number corresponding to the slot period;   outputting a reference signal corresponding to a frequency of the clock signal according to the sample number; and   sampling the data signal according to the clock signal and the reference signal to decode data of the data signal.   
     
     
         16 . The decoding method according to  claim 15 , wherein the data signal is corresponding to a DMX512 protocol. 
     
     
         17 . The decoding method according to  claim 15 , wherein the step of generating the sample number corresponding to the slot period further comprises:
 sampling a first slot of the slots to generate the sample number, wherein the first slot has a start code.   
     
     
         18 . The decoding method according to  claim 15 , wherein the step of generating the sample number corresponding to the slot period further comprises sampling a first slot of the slots to generate the sample number, wherein the first slot has a default code.