US2012026816A1PendingUtilityA1

Defective memory block identification in a memory device

Individually held — no corporate assignee on recordPriority: Aug 31, 2004Filed: Oct 7, 2011Published: Feb 2, 2012
Est. expiryAug 31, 2024(expired)· nominal 20-yr term from priority
G11C 16/04G11C 29/72G11C 2029/4402G11C 29/26G11C 29/44G11C 16/0483
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Claims

Abstract

During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.

Claims

exact text as granted — not AI-modified
1 . A memory device, configured to store in the memory device an indication of a location of a block of memory cells of the device that has been determined to be defective. 
     
     
         2 . The memory device of  claim 1 , wherein the indication is stored in another block of the memory cells of the device that is different than the defective block. 
     
     
         3 . The memory device of  claim 2 , wherein the other block comprises a block of memory cells that has been determined to be free of defects. 
     
     
         4 . The memory device of  claim 1 , wherein the indication comprises a block number. 
     
     
         5 . The memory device of  claim 2 , wherein the indication is stored at an end of the other block. 
     
     
         6 . The memory device of  claim 2 , wherein the other block comprises a first block of memory cells of the memory device determined to be defect free. 
     
     
         7 . The memory device of  claim 1 , wherein the indication of the location comprises indications of locations of a plurality of blocks of memory cells of the device determined to be defective. 
     
     
         8 . The memory device of  claim 1 , wherein the indication is stored at the end of the block of memory cells. 
     
     
         9 . The memory device of  claim 8 , wherein the indication comprises a column of the block of memory cells that contains a defective location. 
     
     
         10 . A memory device comprising a block of memory cells, wherein a programmed pattern of data is stored in a block of memory cells that indicates that the block of memory cells is programmable. 
     
     
         11 . The memory device of  claim 10 , wherein the programmed pattern is stored in the block after the memory device has been tested and it has been determined that the block can be programmed. 
     
     
         12 . The memory device of  claim 10 , wherein the programmed pattern is stored at a defect indication location in the block. 
     
     
         13 . The memory device of  claim 12 , wherein the defect indication location is at the end of the block. 
     
     
         14 . The memory device of  claim 12 , further comprising control circuitry configured to read the defect indication location of the block to determine whether the block is usable. 
     
     
         15 . The memory device of  claim 12 , further comprising control circuitry configured to read the defect indication location of the block to determine whether the block is programmable. 
     
     
         16 . The memory device of  claim 1 , further comprising control circuitry configured to read the indication to determine whether the block is usable. 
     
     
         17 . The memory device of  claim 1 , further comprising control circuitry configured to read the indication to determine whether the block is programmable 
     
     
         18 . A system, comprising:
 a processor; and   a memory device coupled to the processor, wherein an indication of a location of a block of memory cells of the device that has been determined to be defective is stored in the memory device.   
     
     
         19 . A system, comprising:
 a processor; and   a memory device coupled to the processor and comprising a block of memory cells, wherein a programmed pattern of data is stored in a block of memory cells that indicates that the block of memory cells is programmable.   
     
     
         20 . The system of  claim 19 , wherein the block is not programmable if the pattern is missing.

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