Low Cost Testing and Sorting of Integrated Circuits

Abstract

Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster.

1 . A method of testing integrated circuits, comprising:
 a) testing a plurality of integrated circuits, each integrated circuit having permanent non-volatile information and programmable non-volatile information and   b) writing the permanent non-volatile information over the programmable non-volatile information in those integrated circuits that pass testing, wherein the written information matches the permanent non-volatile information.   
     
     
         2 . The method of  claim 1 , wherein the plurality of integrated circuits are in a cluster on a substrate. 
     
     
         3 . The method of  claim 2 , wherein each cluster has external power and data terminals connected to common power and data busses, providing common power supply and data signals to each integrated circuit in the cluster. 
     
     
         4 . The method of  claim 3 , wherein the power and data terminals comprise two power supply pads and a data pad. 
     
     
         5 . The method of  claim 3 , wherein testing the cluster of integrated circuits comprises temporarily providing power, test data, and a clock signal to the cluster. 
     
     
         6 . The method of  claim 2 , further comprising not writing the permanent non-volatile information over the programmable non-volatile information in those integrated circuits that fail to receive or pass testing. 
     
     
         7 . The method of  claim 6 , wherein not writing the permanent non-volatile information over the programmable non-volatile information renders the integrated circuit permanently disabled upon separation from the cluster. 
     
     
         8 . The method of  claim 1 , further comprising not writing the permanent non-volatile information over the programmable non-volatile information in those integrated circuits that fail to receive or pass testing, wherein not writing the permanent non-volatile information over the programmable non-volatile information renders the integrated circuit permanently disabled. 
     
     
         9 . The method of  claim 2 , further comprising sorting the integrated circuits by:
 a) separating the integrated circuits in the cluster;   b) querying the integrated circuits to determine which integrated circuits respond; and   c) discarding the integrated circuits that do not respond.   
     
     
         10 . The method of  claim 1 , wherein each integrated circuit comprises a ROM configured to store the permanent non-volatile information, and an EEPROM configured to store the programmable non-volatile information. 
     
     
         11 . The method of  claim 10 , further comprising determining whether the programmable non-volatile information in the EEPROM matches the permanent non-volatile information in the ROM. 
     
     
         12 . The method of  claim 11 , further comprising determining whether the programmable non-volatile information in the EEPROM matches the permanent non-volatile information in the ROM. 
     
     
         13 . An integrated circuit, comprising:
 a) permanent non-volatile information;   b) programmable non-volatile information; and   c) logic adapted to (i) determine whether the programmable non-volatile information matches the permanent non-volatile information and (ii) permanently disable the integrated circuit when the programmable non-volatile information does not match the permanent non-volatile information.   
     
     
         14 . The integrated circuit of  claim 13 , further comprising power and data busses, each of which is unconnected to a terminal configured for external transmission, connecting the integrated circuit to other neighboring integrated circuits to form a cluster. 
     
     
         15 . The integrated circuit of  claim 13 , comprising a ROM configured to store the permanent non-volatile information, and an EEPROM configured to store the programmable non-volatile information. 
     
     
         16 . The integrated circuit of  claim 15 , wherein the permanent non-volatile information is different from than the programmable non-volatile information prior to being programmed. 
     
     
         17 . A cluster of integrated circuits, comprising:
 a) a plurality of electrically interconnected integrated circuits;   b) common power busses, providing electrical interconnections between integrated circuits in the cluster; and   c) power supply pads connected to the common power busses, wherein the common power busses are configured to be disconnected from the power supply pads upon separation of the integrated circuits.   
     
     
         18 . The cluster of integrated circuits of  claim 17 , wherein each integrated circuit is adjacent to at least one other integrated circuit on a substrate. 
     
     
         19 . The cluster of integrated circuits of  claim 17 , wherein the common power busses are (a) coupled to at least one programmable non-volatile memory and to operating circuitry in each integrated circuit, and (b) configured to be disconnected from the integrated circuits upon separation of the integrated circuits. 
     
     
         20 . The cluster of integrated circuits of  claim 17 , wherein the power supply pads are configured to be disconnected from the common power busses upon separation of the integrated circuits. 
     
     
         21 . The cluster of integrated circuits of  claim 17 , further comprising (i) common data buses and (ii) data pads connected to the common data busses, wherein the common data busses are configured to be disconnected from the data pads upon separation of the integrated circuits.