Defect analysis method of semiconductor device

Abstract

A defect analysis method of semiconductor device, wherein defect percentage data for each of inspection units within a wafer and information pieces regarding manufacturing conditions for the wafer are loaded into a computer; statistical testing of the defect percentage data with respect to the manufacturing conditions is performed using the computer; and results of the statistical testing are collected for each of the information pieces on the manufacturing conditions and outputted from the computer.

1 . A defect analysis method for a semiconductor device,
 wherein
 defect percentage data for each of inspection units within a wafer and information pieces regarding manufacturing conditions for the wafer are loaded into a computer; 
 statistical testing of the defect percentage data with respect to the manufacturing conditions is performed using the computer; and 
 results of the statistical testing are collected for each of the information pieces on the manufacturing conditions and outputted from the computer. 
   
     
     
         2 . The defect analysis method according to  claim 1 , wherein the computer outputs the results of the statistical testing such that the results are sorted for each of the information pieces regarding the manufacturing conditions. 
     
     
         3 . The defect analysis method according to  claim 1 , wherein the computer outputs the results of the statistical testing in the form of map data corresponding to positions within a surface of the wafer. 
     
     
         4 . The defect analysis method according to any one of  claims 1 , wherein the computer receives selection of the information pieces on the manufacturing conditions, and extracts and outputs information regarding the statistical testing with respect to the received information regarding the manufacturing conditions. 
     
     
         5 . The defect analysis method according to any one of  claims 2 , wherein the computer receives selection of the information pieces on the manufacturing conditions, and extracts and outputs information regarding the statistical testing with respect to the received information regarding the manufacturing conditions. 
     
     
         6 . The defect analysis method according to any one of  claims 3 , wherein the computer receives selection of the information pieces on the manufacturing conditions, and extracts and outputs information regarding the statistical testing with respect to the received information regarding the manufacturing conditions. 
     
     
         7 . The defect analysis method according to any one of  claims 1 , wherein each of the information pieces regarding the manufacturing conditions is information for identifying a manufacturing apparatus which has processed the wafer. 
     
     
         8 . The defect analysis method according to any one of  claims 2 , wherein each of the information pieces regarding the manufacturing conditions is information for identifying a manufacturing apparatus which has processed the wafer. 
     
     
         9 . The defect analysis method according to any one of  claims 3 , wherein each of the information pieces regarding the manufacturing conditions is information for identifying a manufacturing apparatus which has processed the wafer. 
     
     
         10 . The defect analysis method according to any one of  claims 4 , wherein each of the information pieces regarding the manufacturing conditions is information for identifying a manufacturing apparatus which has processed the wafer. 
     
     
         11 . A defect analysis method for a semiconductor device, comprising the steps of:
 loading defect percentage data for each of inspection units within a wafer and an information piece for identifying a manufacturing apparatus which has processed the wafer from a database into a computer;   performing statistical testing of the defect percentage data with respect to the manufacturing apparatus using the computer; and   outputting results of the statistical testing for the information on the manufacturing apparatus from the computer in the form of map data corresponding to positions within a surface of the wafer.