Memory Module, Cache System and Address Conversion Method

Abstract

A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips.

1 - 18 . (canceled) 
     
     
         19 . A cache system comprising:
 a non-volatile memory; and   a cache memory,   wherein, after address conversion, said cache memory is utilized for data retrieval in said cache memory.   
     
     
         20 . The cache system according to  claim 19 , wherein an address conversion method by said address conversion is programmable. 
     
     
         21 . An address conversion method,
 wherein, in the case where a storage capacity of a cache memory is 2 N  bytes, a line size address is Line[L−1:0], an index address is Index[I−1:0], and a tag address is Tag[N−1−L−1:0], when address inputted into said cache memory is defined as ADD[N−1:0], ADD[L−1:0] is allowed to correspond to the Line[L−1:0], ADD[N−1:I+L] is allowed to correspond to the Tag[N−1−L−1:0], ADD[I+L−1:L] is allowed to correspond to an address INDX 0 [I−1:0], ADD[I+I+L−1:I+L] is allowed to correspond to an address INDX 1 [I−1:0], and a result SUM[I−1:0] obtained by adding the INDX 0 [I−1:0] and INDX 1 [I−1:0] is allowed to correspond to the Index[I−1:0].   
     
     
         22 . A data processing device comprising:
 a cache memory,   wherein said cache memory is a cache memory in which data is retrieved by utilizing an address converted by the address conversion method according to  claim 21 .   
     
     
         23 . A memory module comprising:
 a cache memory,   wherein said cache memory is a cache memory in which data is retrieved by utilizing an address converted by the address conversion method according to  claim 21 .   
     
     
         24 . The cache system according to  claim 19 , wherein an address conversion method by said address conversion is the address conversion method according to  claim 19 . 
     
     
         25 - 36 . (canceled)