Protocol for refresh between a memory controller and a memory device

Abstract

The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

1 . A method for performing refresh operations in a memory device, the method comprising:
 transitioning the memory device from a first refresh state in which a memory controller controls refreshing for the memory device, to a second refresh state in which the memory device controls the refreshing;   while the memory device is in the second refresh state, sending progress information for the refreshing operations from the memory device to the memory controller; and   while returning from the first refresh state to the second refresh state, using the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.   
     
     
         2 . The method of  claim 1 , wherein the subsequent operations can include read operations, write operations, activate operations, precharge operations and refreshing operations. 
     
     
         3 . The method of  claim 2 , wherein controlling the sequencing of the subsequent operations involves determining from the progress information whether a self-refreshing operation is in process or will occur in the near future, and if not, initiating one or more subsequent memory accesses without having to wait for a self-refreshing operation to complete. 
     
     
         4 . The method of  claim 2 , wherein controlling the sequencing of the subsequent operations involves performing memory operations to other banks in the memory device while a self-refreshing operation completes for a given bank in the memory device. 
     
     
         5 . The method of  claim 1 , wherein transitioning from the first refresh state to the second refresh state involves entering a power-down state, wherein a high-speed interface between the memory controller and the memory device is powered down. 
     
     
         6 . The method of  claim 1 , wherein sending the progress information from the memory device to the memory controller involves using a sideband link to send the progress information. 
     
     
         7 . The method of  claim 1 , wherein transitioning from the first refresh state to the second state involves sending information from the memory controller to the memory device which can be used to determine which rows and banks are to be refreshed next. 
     
     
         8 . The method of  claim 1 , wherein during the first refresh state, a frequency of the refreshing operations is dynamically adjusted to account for changes in junction temperature on the memory device. 
     
     
         9 . The method of  claim 1 , wherein while controlling the sequencing of subsequent operations, the memory controller uses the progress information received from the memory device to determine when an in-procress self-refresh operation actually completes. 
     
     
         10 . A method for supporting refreshing operations during a power-down state in a memory device, the method comprising:
 transitioning the memory device from a normal operating state to a power-down state, wherein a high-speed interface on the memory device is powered down during the power-down state;   wherein transitioning to the power-down state involves receiving row/bank information at the memory device from a memory controller, wherein the row/bank information can be used by the memory device to determine which row/bank is to be refreshed next;   while the memory device is in the power-down state, sending commands to control refreshing operations from the memory controller to the memory device; and   while returning from the power-down state to the normal operating state, if a given bank in the memory device is performing a refreshing operation, initiating memory operations to other banks in the memory device while the refreshing operation for the given bank completes.   
     
     
         11 . A memory system comprising:
 a memory controller to control refreshing operations for the memory device during a first refresh mode;   the memory device coupled to the memory controller, the memory device;   to control refreshing operations internally during a second refresh mode, wherein the memory device includes an interface to send progress information for refreshing operations during the second refresh mode to the memory controller; and   wherein upon returning from the first refresh mode to the second refresh mode, the memory controller is configured to use the progress information received from the memory device to control the sequencing of subsequent operations for the memory device.   
     
     
         12 . The memory system of  claim 11 , wherein the subsequent operations can include read operations, write operations, activate operations, precharge operations and refreshing operations. 
     
     
         13 . The memory system of  claim 12 , wherein while controlling the sequencing of the subsequent operations, the memory controller is configured to determine from the progress information whether a self-refreshing operation is in process or will occur in the near future, and if not, to initiate one or more subsequent memory accesses without having to wait for a self-refreshing operation to complete. 
     
     
         14 . The memory system of  claim 12 , wherein while controlling the sequencing of the subsequent operations, the memory controller is configured to perform memory operations to other banks in the memory device while a self-refreshing operation completes for a given bank in the memory device. 
     
     
         15 . The memory system of  claim 11 , wherein the second refresh state is a low-power state, and wherein a high-speed interface between the memory controller and the memory device is powered down. 
     
     
         16 . The memory system of  claim 11 , wherein the memory device is configured to use a low-power sideband link to send the progress information to the memory controller. 
     
     
         17 . The memory system of  claim 11 , wherein while transitioning from the first refresh mode to the second refresh mode, the memory controller is configured to send information to the memory device, which can be used to determine which rows and banks are to be refreshed next. 
     
     
         18 . The memory system of  claim 11 , wherein during the second refresh state, the memory device is configured to dynamically adjust a frequency of the self-refreshing operations to account for changes in junction temperature on the memory device. 
     
     
         19 . The memory system of  claim 11 , wherein while controlling the sequencing of subsequent operations, the memory controller uses the progress information received from the memory device to determine when an in-procress self-refresh operation actually completes. 
     
     
         20 . A memory device comprising:
 a memory array having a plurality of memory cells;   a first interface to receive a first refresh command and a second refresh command, wherein:
 the first refresh command specifies that the memory device refresh a predetermined row of the plurality of memory cells in the memory array; and 
 the second refresh command specifies that the memory device refresh a plurality of rows in the memory array by automatically incrementing an internal address corresponding to a row of the memory cells currently being refreshed; and 
   a second interface to transmit information corresponding to the row of the memory cells currently being refreshed.   
     
     
         21 . A memory controller comprising:
 an interface to communicate with a memory device; and   a sequencing mechanism to sequence operations for the memory device;   wherein during a first refresh state, the sequencing mechanism is configured to control refreshing operations for the memory device;   wherein during a second refresh state, the sequencing mechanism is configured to allow the memory device to control refreshing operations for the memory device, and the memory controller is configured to receive progress information for such self-refreshing operations from the memory device; and   wherein upon returning from the second refresh state to the first refresh state, the sequencing mechanism is configured to use the progress information received from the memory device to control the sequencing of subsequent operations for the memory device.   
     
     
         22 . The memory controller of  claim 21 , wherein the subsequent operations can include read operations, write operations, activate operations, precharge operations and refreshing operations. 
     
     
         23 . The memory controller of  claim 22 , wherein while controlling the sequencing of the subsequent operations, the sequencing mechanism is configured to determine from the progress information whether a self-refreshing operation is in process or will occur in the near future, and if not, to initiate one or more subsequent memory accesses without having to wait for a self-refreshing operation to complete. 
     
     
         24 . The memory controller of  claim 22 , wherein while controlling the sequencing of the subsequent operations, the sequencing mechanism is configured to perform memory operations to other banks in the memory device while a self-refreshing operation completes for a given bank in the memory device. 
     
     
         25 . The memory controller of  claim 21 , wherein the second refresh state is a low-power state, wherein a high-speed interface between the memory controller and the memory device is powered down. 
     
     
         26 . The memory controller of  claim 21 , wherein the memory controller is configured to receive the progress information through a low-power sideband link between the memory device and the memory controller. 
     
     
         27 . A memory controller comprising:
 a first interface on the memory controller that couples the memory controller to a memory device through a first link; and   a second interface on the memory controller that couples the memory controller to the memory device through a second link;   wherein during a power-down state, the first interface is powered down, and the memory controller is configured to send commands to control refreshing operations to the memory device through the second link;   wherein while transitioning from a normal operating state to the power-down state, the memory controller is configured to send row/bank information to the memory device, wherein the row/bank information can be used by the memory device to determine which rows/bank is to be refreshed next; and   wherein while returning from the power-down state to a normal operating state, if a given bank in the memory device is performing a refreshing operation, the memory controller is configured to initiate memory operations to other banks in the memory device while the refreshing operation for the given bank completes.   
     
     
         28 . A memory device comprising:
 one or more memory banks;   an interface to communicate with a memory controller; and   a self-refreshing mechanism;   wherein during a first refresh state, the self-refreshing mechanism is configured to allow the memory controller to control refreshing operations for the memory device; and   wherein during a second refresh state, the self-refreshing mechanism is configured to:   control refreshing operations for the memory device; and   send progress information for refreshing operations to the memory controller, so that when the memory device returns to the first refresh state, the memory controller can use the progress information to control the sequencing of subsequent operations for the memory device.   
     
     
         29 . The memory device of  claim 28 , wherein the subsequent operations can include activate operations, precharge operations, read operations, write operations and refreshing operations. 
     
     
         30 . The memory device of  claim 28 , wherein while controlling the sequencing of the subsequent operations, the memory controller is configured to determine from the progress information whether a self-refreshing operation is in process or will occur in the near future, and if not, to initiate one or more subsequent memory accesses without having to wait for a self-refreshing operation to complete. 
     
     
         31 . The memory device of  claim 28 , wherein while controlling the sequencing of the subsequent operations, the memory controller is configured to perform memory operations to other banks in the memory device while a self-refreshing operation completes for a given bank in the memory device. 
     
     
         32 . The memory device of  claim 28 , wherein the second refresh state is a low-power state, wherein a high-speed interface between the memory controller and the memory device is powered down. 
     
     
         33 . The memory device of  claim 28 , wherein the memory device is configured to send the progress information to the memory controller through a low-power sideband link between the memory device and the memory controller. 
     
     
         34 . The memory device of  claim 28 , wherein during the second refresh state, the self-refreshing mechanism is configured to dynamically adjust a frequency of the self-refreshing operations to account for changes in junction temperature on the memory device. 
     
     
         35 . A memory controller device for controlling a memory device, the memory controller device comprising:
 an first interface to transmit a first refresh command and a second refresh command, wherein:
 the first refresh command specifies that the memory device refresh a predetermined row of the plurality of memory cells in the memory array; and 
 the second refresh command specifies that the memory device refresh a plurality of rows in the memory array by automatically incrementing an internal address corresponding to a row of the memory cells currently being refreshed; and 
   a second interface to receive information corresponding to the row of the memory cells currently being refreshed.