Semiconductor memory device

Abstract

Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

1 - 5 . (canceled) 
     
     
         6 . A method for controlling a semiconductor memory device having an error correction function of correcting a defective bit, the method comprising:
 counting, as a first value, a. number of error corrections in a first test operation of the semiconductor memory device using a first test pattern, and storing the first value in a storage unit;   counting, as a second value, a number of error corrections in a second test operation of the semiconductor memory device using the first test pattern after a stress test is performed;   comparing the second value with the first value stored in the storage unit; and outputting an alarm in a case where the second value is greater than the first value.