Semiconductor device

Abstract

An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

1 . A semiconductor device comprising:
 a first transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode;   a first wiring over the first gate electrode;   an interlayer film over the first wiring; and   a second wiring over the interlayer film,   wherein a portion of the first gate electrode overlaps with a first channel formation region of the first semiconductor layer,   wherein the first wiring is in contact with the portion of the first gate electrode, and   wherein the second wiring is in contact with the first wiring and overlaps with the portion of the first gate electrode.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein each of the first wiring and the second wiring is provided between the first source electrode and the first drain electrode.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein the first transistor comprises an oxide semiconductor.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein a thickness of the interlayer film is greater than or equal to 10 nm and less than or equal to 100 nm.   
     
     
         5 . The semiconductor device according to  claim 3 ,
 wherein the first wiring is configured to receive a first signal,   wherein the second wiring is configured to receive a second signal, and   wherein the first signal and the second signal have a same potential.   
     
     
         6 . The semiconductor device according to  claim 3 ,
 wherein the first wiring is configured to receive a first signal,   wherein the second wiring is configured to receive a second signal, and   wherein the first signal and the second signal have a same phase.   
     
     
         7 . A semiconductor device comprising:
 a first transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode;   a second transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode;   a first wiring over the first gate electrode and the second gate electrode;   an interlayer film over the first wiring; and   a second wiring over the interlayer film,   wherein a portion of the first gate electrode overlaps with a first channel formation region of the first semiconductor layer,   wherein a portion of the second gate electrode overlaps with a second channel formation region of the second semiconductor layer,   wherein the first wiring is in contact with the portion of the first gate electrode and the portion of the second gate electrode,   wherein the second wiring is in contact with the first wiring, overlaps with the portion of the first gate electrode, and overlaps with the portion of the second gate electrode, and   wherein the first drain electrode and the second drain electrode are electrically connected to each other.   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein each of the first wiring and the second wiring is provided between the first source electrode and the first drain electrode.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein each of the first wiring and the second wiring is provided between the second source electrode and the second drain electrode.   
     
     
         10 . The semiconductor device according to  claim 9 ,
 wherein at least one of the first transistor and the second transistor comprises an oxide semiconductor.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein a thickness of the interlayer film is greater than or equal to 10 nm and less than or equal to 100 nm.   
     
     
         12 . The semiconductor device according to  claim 10 ,
 wherein the first wiring is configured to receive a first signal,   wherein the second wiring is configured to receive a second signal, and   wherein the first signal and the second signal have a same potential.   
     
     
         13 . The semiconductor device according to  claim 10 ,
 wherein the first wiring is configured to receive a first signal,   wherein the second wiring is configured to receive a second signal, and   wherein the first signal and the second signal have a same phase.   
     
     
         14 . A semiconductor device comprising:
 a first transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode;   a second transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode;   a first wiring over the first gate electrode and the second gate electrode;   an interlayer film over the first wiring;   a second wiring over the interlayer film; and   a memory cell comprising:
 a third transistor comprising a third channel formation region, a third gate electrode, a third source electrode, and a third drain electrode; 
 a fourth transistor comprising a fourth channel formation region, a fourth gate electrode, a fourth source electrode, and a fourth drain electrode; and 
 a capacitor, 
   wherein a portion of the first gate electrode overlaps with a first channel formation region of the first semiconductor layer,   wherein a portion of the second gate electrode overlaps with a second channel formation region of the second semiconductor layer,   wherein the first wiring is in contact with the portion of the first gate electrode and the portion of the second gate electrode,   wherein the second wiring is in contact with the first wiring, overlaps with the portion of the first gate electrode, and overlaps with the portion of the second gate electrode,   wherein the first drain electrode and the second drain electrode are electrically connected to each other, and   wherein the first wiring comprising a same material as the third source electrode and the third drain electrode.   
     
     
         15 . The semiconductor device according to  claim 14 ,
 wherein each of the first wiring and the second wiring is provided between the first source electrode and the first drain electrode.   
     
     
         16 . The semiconductor device according to  claim 15 ,
 wherein each of the first wiring and the second wiring is provided between the second source electrode and the second drain electrode.   
     
     
         17 . The semiconductor device according to  claim 16 ,
 wherein at least one of the first transistor, the second transistor, and the third transistor comprises an oxide semiconductor, and   wherein the fourth transistor comprises silicon.   
     
     
         18 . The semiconductor device according to  claim 17 ,
 wherein a thickness of the interlayer film is greater than or equal to 10 nm and less than or equal to 100 nm.   
     
     
         19 . The semiconductor device according to  claim 17 ,
 wherein the first wiring is configured to receive a first signal,   wherein the second wiring is configured to receive a second signal, and   wherein the first signal and the second signal have a same potential.   
     
     
         20 . The semiconductor device according to  claim 17 ,
 wherein the first wiring is configured to receive a first signal,   wherein the second wiring is configured to receive a second signal, and   wherein the first signal and the second signal have a same phase.