Multiple level programming in a non-volatile memory device

Abstract

The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.

1 .- 20 . (canceled) 
     
     
         21 . An electronic system comprising:
 a processor for generating control signals that are transmitted on control connections; and   a memory device, coupled to the processor, for operating in response to the control signals, the memory device comprising:   a memory array comprising a plurality of word lines that are each coupled to a plurality of multiple level memory cells the memory array adapted to receive data as controlled by the control signals; and   a control circuit that receives control signals from the processor and is coupled to program the memory array, the control circuit configured to initially program a first page, with two highest distributions, and subsequently program a second page with lower distributions.   
     
     
         22 . The system of  claim 21  wherein the memory device is a NAND flash memory device. 
     
     
         23 . The system of  claim 21  wherein the memory signals comprise programming and verification commands. 
     
     
         24 . The system of  claim 21  wherein each distribution represents a programmable state for the plurality of memory cells. 
     
     
         25 . The system of  claim 24  wherein the control circuit is configured to program memory cells on the first page in descending order of distributions that begin at the highest distribution. 
     
     
         26 . The system of  claim 24  wherein each state is comprised of two bits. 
     
     
         27 . The system of  claim 21  wherein each of the plurality of memory cells is programmable within four different distributions in response to at least one programming pulse. 
     
     
         28 . The system of  claim 21  wherein the control circuit programs the first and second pages by control of generation of a series of incrementing programming pulses. 
     
     
         29 . The system of  claim 28  wherein the control circuit is further configured to control generation of a verify pulse between each programming pulse. 
     
     
         30 . The system of  claim 21  wherein the control circuit is further configured to program:
 a first set of memory cells of the plurality of memory cells of a word line, each memory cell having a plurality of programmable states wherein each state is represented by a threshold voltage distribution, a second set of memory cells of the word line, and remaining memory cells of the word line wherein the first set of memory cells are programmed to a first threshold voltage distribution, the second set of memory cells are programmed to a second threshold voltage distribution and further wherein the first threshold voltage distribution is greater than the second threshold voltage distribution and the remaining memory cells of the word line are programmed in a decreasing order of threshold voltage distributions.