Voltage sustaining layer wiht opposite-doped island for seminconductor power devices

Abstract

A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

I claim: 
     
         1 . A method of manufacturing a semiconductor device having a voltage sustaining layer with n sub-layers, n being an integer greater than or equal to 2, the method comprising:
 (a) preparing a semiconductor wafer having first and second main surfaces and a region of a first conductivity type proximate the first main surface;   (b) forming an epitaxial layer of the first conductivity type on the first main surface of the semiconductor wafer;   (c) growing an oxide layer on the epitaxial layer;   (d) forming at least one opening in the oxide layer;   (e) implanting a dopant through the at least one opening to form at least one region of a second conductivity type;   (f) removing the oxide layer; and   (g) repeating steps (b)-(f) n−1 times,   the voltage sustaining layer having a width W extending from the first main surface of the semiconductor wafer, such that the at least one region of the second conductivity type of a sub-layer k is spaced from the first main surface of the semiconductor wafer by a distance of kW/n.   
     
     
         2 . The method of  claim 1 , wherein the at least one region of the second conductivity type in one of the n sub-layers is offset in a direction parallel to the first main surface of the semiconductor wafer with respect to the at least one region of the second conductivity type in an adjacent sub-layer 
     
     
         3 . The method of  claim 1 , wherein the at least one region of the second conductivity type in one of the n sub-layers is aligned in a direction parallel to the first main surface of the semiconductor wafer with the at least one region of the second conductivity type in an adjacent sub-layer 
     
     
         4 . The method of  claim 1 , wherein step (a) comprises forming a buffer layer of the first conductivity type on a substrate of the second conductivity type. 
     
     
         5 . The method of  claim 1 , wherein the first conductivity type is one of n-type and p-type and the second conductivity type is the other of n-type and p-type. 
     
     
         6 . The method of  claim 1 , wherein the first region of the first conductivity type has a first doping concentration and the epitaxial layer of the first conductivity type has a second doping concentration different from the first doping concentration.