Structures with increased photo-alignment margins

Abstract

Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

1 - 9 . (canceled) 
     
     
         10 . An integrated circuit, comprising:
 a regularly repeating plurality of electrical devices arranged in an array;   a plurality of conductive interconnects connecting electrical devices of the array, each interconnect having a width, wherein portions of the interconnects extend in spaced, generally parallel relation to one another between first and second spaced planes extending perpendicular to the interconnects and other portions of the interconnects extend in spaced, generally parallel relation to one another between third and fourth spaced planes extending perpendicular to the interconnects, wherein the portions of the interconnects are at an angle relative to the other portions of the interconnects, wherein the other portions of the interconnects are outside the array; and   a plurality of contact structures, each contact structure having a minimum dimension, wherein at least one contact structure contacts each of the interconnects between the third and the fourth spaced planes.   
     
     
         11 . The integrated circuit of  claim 10 , wherein the angle is less than about 90°. 
     
     
         12 . The integrated circuit of  claim 11 , wherein the angle is between about 30-90°. 
     
     
         13 . The integrated circuit of  claim 10 , wherein the contact structures are landing pads. 
     
     
         14 . The integrated circuit of  claim 13 , wherein a separation between interconnect lines between the first and second spaced planes is less a separation between interconnect lines between the third and the fourth spaced planes. 
     
     
         15 . The integrated circuit of  claim 14 , wherein a minimum dimension of the landing pads is about 0.30 μm. 
     
     
         16 . The integrated circuit of  claim 14 , wherein a minimum distance between the landing pads and an interconnect is about 0.20 μm or less. 
     
     
         17 . The integrated circuit of  claim 16 , wherein a minimum distance between the landing pads and an interconnect is about 0.10 μm or less. 
     
     
         18 . The integrated circuit of  claim 16 , wherein a minimum distance between landing pads is about 0.40 μm or less. 
     
     
         19 . The integrated circuit of  claim 18 , wherein a minimum distance between landing pads is about 0.25 μm or less. 
     
     
         20 . The integrated circuit of  claim 10 , wherein the array is a gate array for a logic. 
     
     
         21 . A memory device, comprising:
 an array region comprising a plurality of memory cells arranged in rows, wherein each of a plurality of conductive lines connect a row of memory cells; and   a periphery region comprising landing pads, wherein each landing pad is in contact with one of the plurality of conductive lines, wherein the conductive lines extend into both the array region and the periphery region, wherein a spacing between neighboring conductive lines in the periphery region is greater than a spacing between neighboring conductive lines in the array region.   
     
     
         22 . The memory device of  claim 21 , wherein the spacing between neighboring conductive lines in the periphery region is between about 1.5 to about 3 times greater than the spacing between neighboring conductive lines in the array region. 
     
     
         23 . The memory device of  claim 22 , wherein segments of the conductive lines in the peripheral region extend at an angle of between about 30-90° relative to segments of the conductive lines in the interior region. 
     
     
         24 . The memory device of  claim 21 , wherein a pitch of the conductive lines is about 200 nm or less. 
     
     
         25 . The memory device of  claim 24 , wherein the pitch of the conductive lines is less than about 100 nm. 
     
     
         26 . The memory device of  claim 25 , wherein a minimum dimension of the landing pads is about 0.30 μm. 
     
     
         27 . The memory device of  claim 21 , wherein the conductive lines have an edge roughness less than about 5 nm rms. 
     
     
         28 . The memory device of  claim 27 , wherein the edge roughness is about 1-2 nm rms. 
     
     
         29 . The memory device of  claim 27 , wherein the conductive lines have a width of about 50 nm. 
     
     
         30 . The memory device of  claim 21 , wherein the memory device is a DRAM. 
     
     
         31 . The memory device of  claim 21 , wherein the memory device is a non-volatile memory having repetitive cell arrays. 
     
     
         32 . The memory device of  claim 31 , wherein the memory device is a flash memory chip. 
     
     
         33 . The memory device of  claim 21 , wherein the conductive line is a word line. 
     
     
         34 . The memory device of  claim 21 , wherein the conductive line is a bit line.