Digital to analog converters having circuit architectures to overcome switch losses

Abstract

A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. A first force switch may be coupled to an output of a first operational amplifier and an associated sense switch may be coupled to an inverting input of the first operational amplifier. A second force switch may be coupled to an output of a second operational amplifier and an associated sense switch may be coupled to an inverting input of the second operational amplifier. The force switches may provide selectively conductive paths to permit either operational amplifier to drive a given cell.

1 . A digital to analog converter (DAC), comprising:
 a pair of operational amplifiers, each having a first input to couple to a respective source voltage; and   a plurality of switch-controlled cells, each cell comprising:
 a resistor, 
 a first force/sense pair of switches coupled to each other in series and rendered conductive in response to a first state of a control signal; 
 a second force/sense pair of switches coupled to each other in series and rendered conductive in response to a second state of a control signal. 
   
     
     
         2 . The DAC of  claim 18 , wherein
 the sense switches within the first force/sense pair have conductive resistances that scale in accordance with a weight with which the sense switches' cell contributes, when activated, to an output voltage of the DAC, and   the sense switches within the second force/sense pair have conductive resistances that scale in accordance with a weight with which the sense switches' cell contributes, when activated, to the output voltage of the DAC.   
     
     
         3 . The DAC of  claim 1 , wherein in operation multiple first force/sense pairs can be switched to the first operational amplifier and multiple second force/sense pairs can be switched to the second operational amplifier simultaneously. 
     
     
         4 . The DAC of  claim 1 , wherein the DAC has a segmented architecture. 
     
     
         5 . The DAC of  claim 18 , wherein resistances of the resistors of all the cells are equal to each other. 
     
     
         6 . The DAC of  claim 4 , wherein resistances of the sense switches of the first force/sense pair are equal to the resistances of the first force switches and resistances of all the sense switches of the second pairs are equal to the resistances of the second force switches. 
     
     
         7 . The DAC of  claim 18 , wherein the DAC has a binary weighted R2R architecture. 
     
     
         8 . The DAC of  claim 18 , wherein
 resistances of the sense switches of the first pairs escalate according to a binary weighting of the switches' cell assignments, and   resistances of the sense switches of the second pairs escalate according to the binary weighting of the switches' cell assignments.   
     
     
         9 . The DAC of  claim 7 , wherein resistances of the resistors of all the cells escalate according to a binary weighting of the resistors' cell assignments. 
     
     
         10 . The DAC of  claim 1 , wherein the DAC has an architecture that is a hybrid of a binary weighted R2R architecture and a segmented architecture. 
     
     
         11 . The DAC of  claim 1 , wherein the first force/sense pair of switches are PMOS transistors and the second force/sense pair of switches are NMOS transistors. 
     
     
         12 . The DAC of  claim 18 , further comprising:
 a second pair of operational amplifiers, each having a first input coupled to an input of a respective one of the first pair of operational amplifiers,   a second plurality of switch-controlled cells, each cell comprising:
 a resistor, 
 a first force/sense pair of switches coupled to each other in series and rendered conductive in response to a first state of a control signal, an intermediate node of the first pair of switches coupled to the resistor, a force switch of the first pair coupled to an output of a first one of the second pair of operational amplifiers, and a sense switch of the first pair coupled to a second input of the first one of the second pair of operational amplifiers, and 
 a second force/sense pair of switches coupled to each other in series and rendered conductive in response to a second state of a control signal, an intermediate node of the second pair of switches coupled to the intermediate node of the first pair of switches, a force switch of the second pair coupled to an output of a second one of the second pair of operational amplifiers, and a sense switch of the second pair coupled to a second input of the second one of the second pair of operational amplifiers. 
   
     
     
         13 . The DAC of  claim 12 , wherein
 the first pair and second pair of operational amplifiers define respective ranges,   resistances of select first sense switches of the cells in each range escalate according to a binary weight corresponding to the cell's contribution, when activated, to an output voltage of the DAC, and   resistances of select second sense switches in each range escalate according to a binary weight corresponding to the cell's contribution, when activated, to an output voltage of the DAC.   
     
     
         14 . A digital to analog converter (DAC), comprising:
 plural pairs of operational amplifiers, each pair defining a respective range of the DAC;   a plurality of switch controlled cells for each range, each cell comprising:
 a resistor, 
 a first force/sense pair of switches coupled to each other in series and rendered conductive in response to a first state of a respective control signal input of the first operational amplifier in the respective range, and 
 a second force/sense pair of switches coupled to each other in series and rendered conductive in response to a second state of a control signal. 
   
     
     
         15 . The DAC of  claim 19 , wherein across all cells of at least one of the ranges:
 resistances of the first sense switches escalate according to a binary weight corresponding to the cell's respective contribution, when activated, to an output voltage of the DAC, and   resistances of the second sense switches escalate according to the binary weight corresponding to the cell's respective contribution, when activated, to the output voltage of the DAC.   
     
     
         16 . The DAC of  claim 19 , wherein across select cells of at least one of the ranges:
 resistances of the first sense switches escalate according to a binary weight corresponding to the cell's respective contribution, when activated, to an output voltage of the DAC, and   resistances of the second sense switches escalate according to the binary weight corresponding to the cell's respective contribution, when activated, to the output voltage of the DAC.   
     
     
         17 . The DAC of  claim 15 , wherein a base resistance of the first sense switches and a base resistance of the second sense switches reset in each range. 
     
     
         18 . The DAC of  claim 1 , wherein
 an intermediate node of the first pair of switches is coupled to the resistor, a force switch of the first pair is coupled to an output of the first amplifier, and a sense switch of the first pair is coupled to a second input of the first operational amplifier, and   an intermediate node of the second pair of switches is coupled to the intermediate node of the first pair of switches, a force switch of the second pair is coupled to an output of the second amplifier, and a sense switch of the second pair is coupled to a second input of the second operational amplifier.   
     
     
         19 . The DAC of  claim 14 , wherein
 an intermediate node of the first pair of switches is coupled to the resistor, a force switch of the first pair is coupled to an output of the first operational amplifier in the respective range, and a sense switch of the first pair is coupled to a second input of the first operational amplifier in the respective range, and   an intermediate node of the second pair of switches is coupled to the intermediate node of the first pair of switches, a force switch of the second pair is coupled to an output of the second operational amplifier in the respective range, and a sense switch of the second pair is coupled to a second input of the second operational amplifier in the respective range.