Split wave compensation for open stubs

Abstract

In accordance with a first embodiment, the present invention provides a circuit substrate comprising a first surface; a second surface; a first via having a first end near said first surface and a second end near said second surface; a second via having a first end near said first surface and a second end near said second surface; a first conductive element electrically coupling said first end of said first via and said first end of said second via; a second conductive element electrically coupling said second end of said first via and said second end of said second via; an input signal line coupled to said first via; and an output signal line coupled to said second via.

1 - 11 . (canceled) 
     
     
         12 . A method comprising:
 providing a circuit substrate having a first surface and a second surface;   forming a first via through said circuit substrate, said first via having a first end near said first surface and a second end near said second surface;   forming a second via through said circuit substrate, said second via having a first end near said first surface and a second end near said second surface;   providing a first conductive element;   providing a second conductive element; electrically coupling said first end of said first via to said first end of said second via using said first conductive element;   electrically coupling said second end of said first via to said second end of said second via using said second conductive element;   providing an input node to said first via; and   providing an output node to said second via.   
     
     
         13 . A method according to  claim 12 , wherein said input node includes an intermediate layer of said circuit substrate. 
     
     
         14 . A method according to  claim 12 , wherein providing an input node to said first via includes coupling said input node to said first via between said first end and said second end. 
     
     
         15 . A method according to  claim 12 , wherein said output node includes an intermediate conductive layer of said circuit substrate. 
     
     
         16 . A method according to  claim 15 , wherein providing an output node to said second via includes coupling said output node to said second via between said first end and said second end. 
     
     
         17 . A method according to  claim 12 , wherein said input signal line and said output signal line have substantially equal characteristic impedance; and said first via, said second via, said first conductive element, and said second conductive element have substantially equal characteristic impedance of substantially two times the characteristic impedance of the input signal line. 
     
     
         18 . A method according to  claim 12 , wherein at least one of said first conductive element and said second conductive element includes a microstrip. 
     
     
         19 . A method according to  claim 12 , wherein the input node includes at least one through-hole pin connector. 
     
     
         20 . A method according to  claim 19 , wherein said through-hole pin connector is suitable to receive a backplane connector. 
     
     
         21 . A method according to  claim 12 , wherein the first conductive element and the second conductive element are designed so that the delay of a first signal path from the input node via said first conductive element to the output node is substantially equal to the delay of a second signal path from the input node via said second conductive element to the output node. 
     
     
         22 . A method according to  claim 12 , wherein said first via has a characteristic impedance substantially equal to the characteristic impedance of said second via. 
     
     
         23 . A method comprising:
 providing a circuit substrate having a first surface and a second surface;   forming a first via through said circuit substrate, said first via having a first end near said first surface and a second end near said second surface;   forming a second via through said circuit substrate, said second via having a first end near said first surface and a second end near said second surface;   providing a first conductive element;   providing a second conductive element;   electrically coupling said first end of said first via to said first end of said second via using said first conductive element;   electrically coupling said second end of said first via to said second end of said second via using said second conductive element;   providing an input node to said first via;   providing an output node to said second via, wherein said input node and said output node are electrically coupled by a first conductive path through said first conducitive element and wherein said input node and said output node are electrically coupled by a second conductive path through said second conductive element;   conducting a first portion of a signal between said input node and said output node through said first conductive path; and   conducting a second portion of said signal between said input node and said output node through said second conductive path, wherein the first conductive path has substantially the same delay as said second conductive path.   
     
     
         24 . A method according to  claim 23 , wherein said input node includes a conductive layer formed on an intermediate layer of said circuit substrate. 
     
     
         25 . A method according to  claim 24 , wherein said input node is physically coupled to said first via between said first end and said second end. 
     
     
         26 . A method according to  claim 23 , wherein said output node includes a conductive layer formed on an intermediate layer of said circuit substrate. 
     
     
         27 . A method according to  claim 26 , wherein said output node is physically coupled to said second via between said first end and said second end. 
     
     
         28 . A method according to  claim 23 , wherein at least one of said first conductive element and said second conductive element includes a microstrip. 
     
     
         29 . A method according to  claim 23 , wherein at least one of said first via and said second via includes a through-hole pin connector via. 
     
     
         30 . A method substrate according to  claim 29 , wherein said through-hole pin connector via is suitable to receive a backplane connector pin. 
     
     
         31 . A method comprising:
 providing a circuit substrate having a first surface and a second surface;   forming a first via through said circuit substrate, said first via having a first end near said first surface and a second end near said second surface;   forming a second via through said circuit substrate, said second via having a first end near said first surface and a second end near said second surface, and wherein said first via has a characteristic impedance substantially equal to the characteristic impedance of said second via;   providing a first conductive element;   providing a second conductive element;   electrically coupling said first end of said first via to said first end of said second via using said first conductive element;   electrically coupling said second end of said first via to said second end of said second via using said second conductive element;   providing an input node to said first via;   providing an output node to said second via, wherein said input node and said output node are electrically coupled by a first conductive path through said first conducitive element and wherein said input node and said output node are electrically coupled by a second conductive path through said second conductive element;   conducting a first portion of a signal between said input node and said output node through said first conductive path; and   conducting a second portion of said signal between said input node and said output node through said second conductive path.