High Dynamic Range CMOS Pixel and Method of Operating Same

Abstract

A method of operating a CMOS pixel is disclosed. The CMOS pixel includes a photodiode (PPD), a transfer gate coupled to the PPD, and an anti-blooming drain coupled to the transfer gate. A potential barrier is formed between a potential well underlying the PPD and the transfer gate. Charge is accumulated in the potential well in response to electromagnetic radiation during a first integration time. Excess charge is removed from the potential well to the anti-blooming drain that exceeds the first potential barrier. A size of the potential barrier is increased. Charge is accumulated in the potential well during a second integration time.

What is claimed is: 
     
         1 . A method of operating a CMOS pixel, wherein the CMOS pixel comprises a photodiode (PPD), a transfer gate coupled to the PPD, and an anti-blooming drain coupled to the transfer gate, the method comprising:
 forming a potential barrier between a potential well and the transfer gate;   accumulating charge in the potential well in response to electromagnetic radiation during a first integration time;   removing excess charge from the potential well to the anti-blooming drain that exceeds the potential barrier;   increasing a size of the potential barrier; and   accumulating charge in the potential well during a second integration time.   
     
     
         2 . The method of  claim 1 , wherein the accumulated charge remains within the potential well during the second integration time such that a response signal of the CMOS pixel remains within a linear region. 
     
     
         3 . The method of  claim 1 , wherein increasing the size of the potential barrier comprises increasing a magnitude of a potential applied to the transfer gate from a first level before the first integration time to a second level at the second integration time. 
     
     
         4 . The method of  claim 1 , wherein the size of the potential barrier is increased non-linearly as a function of time. 
     
     
         5 . The method of  claim 4 , wherein the size of the potential barrier is increased in discrete steps over time. 
     
     
         6 . The method of  claim 4 , wherein the size of the potential well is increased continuously over time. 
     
     
         7 . The method of  claim 1 , wherein the second integration time is shorter than the first integration time. 
     
     
         8 . The method of  claim 1 , further comprising operating the transfer gate with a plurality of narrow pulses. 
     
     
         9 . The method of  claim 8 , wherein voltage applied to the transfer gate is adjusted for each of the plurality of narrow pulses. 
     
     
         10 . The method of  claim 8 , wherein spacing in time for each of the plurality of narrow pulses is reduced for a subsequent sub-integration time. 
     
     
         11 . A method of operating a CMOS pixel, wherein the CMOS pixel comprises a photodiode (PPD), a transfer gate coupled to the PPD, and an anti-blooming drain coupled to the transfer gate, the method comprising:
 (a) coupling a capacitor to the sense node;   (b) forming a potential barrier between a potential well underlying the PPD and the transfer gate;   (c) accumulating charge in the potential well in response to electromagnetic radiation during a first integration time;   (d) removing excess charge from the potential well to the anti-blooming drain that exceeds the first potential barrier;   (e) increasing a size of the potential barrier;   (f) accumulating charge in the potential well during a second integration time; and   (g) decoupling the capacitor from the sense node.   
     
     
         12 . The method of  claim 11 , wherein steps (a)-(g) are performed over two consecutive frames. 
     
     
         13 . The method of  claim 11 , wherein steps (a)-(g) are performed within a single frame. 
     
     
         14 . The method of  claim 11 , wherein the accumulated charge remains within the potential well during the second integration time such that a response signal of the pixel remains within a linear region. 
     
     
         15 . The method of  claim 11 , wherein increasing the size of the potential barrier comprises increasing a magnitude of the potential applied to the transfer gate from a first level before the first integration time to a second level before the second integration time period. 
     
     
         16 . The method of  claim 11 , wherein the size of the potential barrier is increase non-linearly as a function of time. 
     
     
         17 . The method of  claim 16 , wherein the size of the potential barrier is increased in discrete steps over time. 
     
     
         18 . The method of  claim 16 , where the size of the potential well is increased continuously over time. 
     
     
         19 . The method of  claim 11 , wherein the second integration time is shorter than the first integration time.