Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor

Abstract

A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.

What is claimed is: 
     
         1 . A processor comprising:
 a command first-in-first-out (FIFO) to store one or more commands;   cryptographic cores;   same-context-command FIFOs configured to store cipher algorithm commands of a same context, each of the same-context-command FIFOs coupled to a corresponding one of the cryptographic cores; and   a scheduler being coupled to each of the cryptographic cores.   
     
     
         2 . The processor of  claim 1  wherein the cryptographic cores corresponds to a first plurality of cryptographic cores in a first core group and the processor further comprises a plurality of core groups, each of the core groups coupled to the command FIFO. 
     
     
         3 . The processor of  claim 1  wherein the cryptographic cores corresponds to a first plurality of cores in a first core group and the processor further comprises:
 a plurality of core groups; and 
 the command FIFO corresponds to a first one of a plurality of command FIFOs, each of the plurality of command FIFOs coupled to a corresponding one of the plurality of core groups. 
 
     
     
         4 . The processor of  claim 3  wherein the same context command FIFOs is provided such that each of the cryptographic cores in the plurality of core groups is coupled to a corresponding one of the same-context-command FIFOs. 
     
     
         5 . The processor of  claim 1  wherein the scheduler is configured to receive a command from the command FIFO and to assign the command to one of the cryptographic cores. 
     
     
         6 . The processor of  claim 1  wherein the scheduler is adapted to receive a command from the command FIFO and to determine which of the cryptographic cores is processing a command and in response to one of the cryptographic cores in the core group processing a command, to determine if the command received from the command FIFO is in the same context as the command being processed by the core. 
     
     
         7 . The processor of  claim 1  wherein the cipher algorithm commands comprise at least one of MD5 commands, 3DES commands or SHAT commands. 
     
     
         8 . A network comprising:
 a first node having a processor, the network processor comprising:   a command first-in-first-out (FIFO) to store one or more commands;   cryptographic cores;   same context command FIFOs, each of the same context command FIFOs coupled to a corresponding one of the cryptographic cores; and   a scheduler coupled to the command FIFO and to each of the cryptographic; and   an interface configured to couple the first node to another node.   
     
     
         9 . The network of  claim 8  further comprising:
 a network communication path coupled to the first node; 
 a second node having a processor, the network processor comprising: 
 a command FIFO to store one or more commands; 
 a plurality of cores; 
 a like plurality of same context command FIFOs, each of the plurality of same context command FIFOs coupled to a corresponding one of the first plurality of cores; and 
 a scheduler coupled to the command FIFO and to each of the first plurality of cores in the core group; and 
 an interface coupled to the first node through the network communication path. 
 
     
     
         10 . The network of  claim 8  wherein the cipher algorithm commands comprises at least one of MD5 commands, 3DES commands or SHAT commands. 
     
     
         11 . A processor comprising:
 (a) cryptographic acceleration units, each of the cryptographic acceleration units comprising:
 (1) a command first-in-first-out (FIFO) queue to store one or more commands; 
 (2) cryptographic cores; 
 (3) same-context command FIFO queues, each of the same context command FIFO queues coupled to a corresponding one of the cryptographic cores; and 
 (4) a scheduler coupled to the command FIFO queue and to each of the cryptographic cores. 
   
     
     
         12 . The processor of  claim 11  further comprising:
 a global FIFO queue having an input adapted to receive commands directed toward at least one of the plurality of cryptographic acceleration units and having an output; and 
 a global scheduler having an input coupled to the output of the global FIFO queue and having an output adapted to provide a data path to each of the plurality of cryptographic acceleration units. 
 
     
     
         13 . The processor of  claim 12  wherein the cryptographic cores form a first core group and wherein the processor further comprises a plurality of core groups, each of plurality of core groups coupled to the global scheduler.