Nonvolatile Memory Device and Method of Manufacturing the Same

Abstract

A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

What is claimed is: 
     
         1 . A nonvolatile memory device, comprising:
 first gate patterns formed over a semiconductor substrate of a cell region and second gate patterns and third gate patterns formed over the semiconductor substrate of the peripheral region;   cell junction regions formed in the semiconductor substrate on both sides of each of the first gate patterns; and   peripheral junction regions formed in the semiconductor substrate on both sides of each of the second gate patterns including lower portions of the third gate patterns.   
     
     
         2 . The nonvolatile memory device of  claim 1 , wherein the second gate patterns are formed between the third gate patterns. 
     
     
         3 . The nonvolatile memory device of  claim 1 , wherein a width of the third gate patterns is narrower than that of the first gate patterns. 
     
     
         4 . The nonvolatile memory device of  claim 1 , wherein a width of the third gate patterns is narrower than that of the second gate patterns. 
     
     
         5 . The nonvolatile memory device of  claim 1 , wherein the first gate patterns comprises a source select transistor, a drain select transistor, and a plurality of memory cells. 
     
     
         6 . The nonvolatile memory device of  claim 1 , wherein:
 the second gate patterns comprise first driving transistor gates formed in a first peripheral region of the semiconductor substrate and second driving transistor gates formed in a second peripheral region of the semiconductor substrate; and   the third gate patterns comprise first barrier dummy patterns formed on both sides of the first driving transistor gate in the first peripheral region and second barrier dummy patterns formed on both sides of the second driving transistors in the second peripheral region.   
     
     
         7 . The nonvolatile memory device of  claim 6 , wherein the first peripheral junction regions formed of a P-type and the second peripheral junction regions formed of an N-type. 
     
     
         8 . The nonvolatile memory device of  claim 6 , wherein a first width between the first driving transistor gates and the first barrier dummy patterns is narrower than a second width between the second driving transistor gates and the second barrier dummy patterns. 
     
     
         9 . A method of manufacturing a nonvolatile memory device, comprising:
 forming first gate patterns over a semiconductor substrate of a cell region and forming second gate patterns and third gate patterns over the semiconductor substrate of a peripheral region;   forming junction region in the semiconductor substrate on both sides of each of the first gate patterns; and   forming peripheral junction regions in the semiconductor substrate on both sides of each of the second gate patterns including lower portions of the third gate patterns.   
     
     
         10 . The method of  claim 9 , wherein the third gate patterns are formed between the third gate patterns. 
     
     
         11 . The method of  claim 9 , wherein a width of the second gate patterns is narrower than that of the second gate patterns. 
     
     
         12 . The method of  claim 9 , wherein a width of the third gate patterns is narrower than that of the second gate patterns. 
     
     
         13 . The method of  claim 9 , wherein the first gate patterns comprise a source select transistor, a drain select transistor, and a plurality of memory cells. 
     
     
         14 . The method of  claim 9 , wherein:
 the second gate patterns comprise first driving transistor gates formed in a first peripheral region of the semiconductor substrate and second driving transistor gates formed in a second peripheral region of the semiconductor substrate; and   the third gate patterns comprise first barrier dummy patterns formed on both sides of the first driving transistor gates in the first peripheral region and second barrier dummy patterns formed on both sides of the second driving transistor gates in the second peripheral region.   
     
     
         15 . The method of  claim 14 , wherein the first peripheral junction regions formed of a P-type and the second peripheral junction regions formed of an N-type. 
     
     
         16 . The method of  claim 9 , wherein a first width between the first driving transistor gates and the first barrier dummy patterns is narrower than a second width between the second driving transistor gates and the second barrier dummy patterns. 
     
     
         17 . The method of  claim 14 , wherein the formation of the peripheral junction region comprises:
 implanting P-type impurity ions into the first and second peripheral regions and the cell region;   implanting N-type impurity ions into the second peripheral region and the cell array region so that the P-type impurity ions implanted into the second peripheral region and the cell region are offset from each other; and   implanting the N-type impurity ions into the second peripheral region so that the implantation of the N-type impurity ions into the first peripheral region and the cell array region is blocked.   
     
     
         18 . The method of  claim 17 , wherein the implantation of the P-type impurity ion is performed at an angle of arctangent (h/l 1 ) to 90°. 
     
     
         19 . The method of  claim 17 , wherein the implantation of the N-type impurity ions so that the P-type impurity ions implanted into the second peripheral region and the cell region is offset is performed at an angle of more than arctangent (h/l 3 ) to less than arctangent (h/l 1 ). 
     
     
         20 . The method of  claim 17 , wherein the implantation of the N-type impurity ions into the second peripheral region so that the implantation of the N-type impurity ions into the first peripheral region and the cell region is blocked is performed at an angle of more than arctangent (h/l 2 ) to less than arctangent (h/l 4 ). 
     
     
         21 . The method of  claim 17 , wherein the formation of the junction regions is performed by implanting the N-type impurity ions into the cell array region at an angle of more than arctangent (h/l 3 ) to less than arctangent (h/l 1 ).