Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

Abstract

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

What is claimed is: 
     
         1 . A semiconductor chip having a via hole comprising:
 a metal wire, at least a portion of which is in the via hole; and   a filler filling the via hole having the metal wire therein, wherein a first end portion of the metal wire is exposed out of the filler.   
     
     
         2 . The semiconductor chip of  claim 1 , further comprising:
 a circuit board having a portion formed with a metal pad, wherein the circuit board is disposed on one surface of the semiconductor chip so as to electrically connect the metal pad to a portion of the metal wire excluding the first end portion.   
     
     
         3 . The semiconductor chip of  claim 2 , wherein the circuit board comprises a polymer layer with bending and adhesive properties, and wherein a stack via is formed in the circuit board to expose a portion of the metal pad that is not in contact with the metal wire. 
     
     
         4 . The semiconductor chip of  claim 1 , wherein the metal wire comprises copper having a cross-sectional shape resembling a T. 
     
     
         5 . The semiconductor chip of  claim 1 , wherein the filler is an underfill material comprising epoxy or a material including polymer. 
     
     
         6 . A semiconductor package comprising:
 first and second semiconductor chips, each chip having a via hole between the first and second surfaces of the chip comprising:
 a metal wire, at least a portion of which is in the via hole; and 
 a filler filling the via hole having the metal wire therein, wherein a first end portion of the metal wire is exposed from the first surface and a second end portion is exposed from the second surface, 
   wherein the first end portion of the metal wire of the first chip is electrically connected to the second end portion of the metal wire of the second chip.   
     
     
         7 . The semiconductor package of  claim 6 , wherein the first end portion of each chip protrudes out of the first surface of each chip and wherein the protruding first end portion of the metal wire of the first chip is electrically connected to the second end portion of the metal wire of the second chip by a solder ball. 
     
     
         8 . The semiconductor package of  claim 7 , wherein each semiconductor chip further comprises:
 a circuit board having a portion formed with a metal pad, wherein one surface of the circuit board is disposed at the second surface of the chip so as to electrically connect the metal pad to the second end portion of the metal wire; and   a stack via formed on the other surface of the circuit board so as to expose a part of the metal pad.   
     
     
         9 . The semiconductor package of  claim 7 , wherein the metal wire comprises copper having a cross-sectional shape resembling a T. 
     
     
         10 . The semiconductor package of  claim 7 , wherein the filler is an underfill material comprising epoxy or a material including polymer. 
     
     
         11 . A method for fabricating a semiconductor chip having a via hole, comprising:
 preparing a circuit board comprising a metal pad formed therein;   attaching a second end portion of a metal wire to the metal pad of the circuit board;   positioning the metal wire in the via hole; and   filling the via hole with a filler so as to expose a first end portion of the metal wire out of the filler.   
     
     
         12 . The method of fabricating a semiconductor chip having a via hole, wherein the first end portion protrudes out of a surface of the semiconductor chip. 
     
     
         13 . The method of  claim 12 , wherein the circuit board comprises a polymer layer with bending and adhesive properties. 
     
     
         14 . The method of  claim 12 , wherein the metal wire comprises copper having a cross-sectional shape resembling a T shape. 
     
     
         15 . The method of  claim 12 , wherein the filler is an underfill material comprising epoxy or a material including polymer. 
     
     
         16 . The method of  claim 12 , further comprising:
 after filling the via hole with the filler, removing the circuit board from the chip such that the metal wire is held in the via hole by the filler.   
     
     
         17 . The method of  claim 12 , further comprising:
 after filling the via hole with the filler, etching a portion of the circuit board to form a stack via that exposes a portion of the metal pad therethrough.   
     
     
         18 . The method of  claim 17 , wherein the stack via is formed through an etch method using a laser. 
     
     
         19 . A method of fabricating a semiconductor package, comprising:
 fabricating first and second semiconductor chips, wherein each chip having a via hole is fabricated by a method comprising:
 preparing a circuit board comprising a metal pad formed therein; 
 attaching a second end portion of a metal wire to the metal pad of the circuit board; 
 positioning the metal wire in the via hole; and 
 filling the via hole with a filler so as to expose a first end portion of the metal wire out of the filler such that the first end portion protrudes out of a surface of the semiconductor chip; and 
   
     
     
         20 . The method of  claim 19 , further comprising:
 connecting the first end portion of the metal wire of the first semiconductor chip to the second end portion of the metal wire of the second semiconductor chip by a solder ball.   
     
     
         21 . The method of  claim 19 , wherein each semiconductor chip further comprises:
 a circuit board having a portion formed with a metal pad, one surface of the circuit board is disposed at the second surface of the chip so as to electrically connect the metal pad to the second end portion of the metal wire; and   a stack via formed on the other surface of the circuit board so as to expose a portion of the metal pad,   wherein the first end portion of the metal wire of the first semiconductor chip is connected to the portion of the metal pad of the second semiconductor chip exposed through the stack via.