Method of manufacturing an integrated circuit and photosensor cell with selectively silicided gates

Abstract

The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

1 . A CMOS active pixel image sensor, comprising:
 an array of pixels, at least one pixel of the array bounded at least partially by an isolation region and comprising:   a p-n junction photodiode to produce photo-generated charge;   a floating diffusion node;   a transfer transistor, including a polysilicon transfer gate, adjacent to the photodiode and to the node, the transfer configured to transfer the charge from the photodiode to the node;   a reset transistor, including a polysilicon reset gate, coupled to the node and to an n+ diffusion region configured to be coupled to a voltage source, the reset transistor configured to transfer voltage from the voltage source to the node;   a source follower transistor, including a polysilicon source follower gate, coupled to the node; and   silicide located on a surface of each one of the polysilicon transfer gate, the polysilicon reset gate, and the polysilicon source of the photodiode and a surface of the node;   a readout circuit configured to provide correlated sampling of the pixel;   an analog-to-digital converter; and   image processing circuitry.   
     
     
         2 . The image sensor of  claim 1 , further comprising a load transistor coupled to a row select transistor and a ground source. 
     
     
         3 . A CMOS active pixel imager, comprising:
 an array of pixels, at least one pixel of the array comprising:   a shallow trench isolation region;   a photodiode having a surface region free of silicide;   a transfer transistor to transfer charge from the photodiode to a node, the transfer transistor having a silicided gate and having a surface of a source/drain region substantially free of silicide;   a reset transistor coupled between the node and the voltage source, the reset transistor having a silicided gate and having a surface of a source/drain region substantially free of silicide; and   a source follower transistor having a silicided gate coupled to the node and having a surface of a source/drain region substantially free of silicide;   a readout circuit configured to provide correlated sampling of each pixel;   an analog-to-digital converter; and   image processing circuitry.   
     
     
         4 . The imager of  claim 3 , further comprising a load transistor coupled to a row select transistor. 
     
     
         5 . A camera system, comprising:
 a bus;   a processor;   random access memory coupled to the processor via the bus;   a CMOS active pixel imager coupled to the processor via the bus, the imager comprising a plurality of pixels each containing silicided transistor gates, transistor source/drain regions free from silicide, a photodiode, and shallow trench isolation, the imager configured to perform correlated sampling of each pixel, analog-to-digital conversion of the output of each pixel, and image processing.   
     
     
         6 . A CMOS imager, comprising:
 an array of pixels, at least one pixel comprising:   a photo-collection region to accumulate photo-generated charge, wherein silicide is substantially absent from a surface of the photosensor;   a transfer transistor to transfer the charge from the photo-collection region to a storage node, wherein the transfer transistor includes a polysilicon transfer gate comprising silicide and the storage node is substantially free of silicide.   
     
     
         7 . The CMOS imager of  claim 6 , further comprising a readout circuit coupled to the array to receive an output signal corresponding to the charge on the node. 
     
     
         8 . The CMOS imager of  claim 6 , wherein the at least one pixel further comprises a reset transistor coupled to the node, wherein the reset transistor includes a polysilicon reset gate comprising opaque silicide. 
     
     
         9 . The CMOS imager of  claim 8 , wherein the at least one pixel further comprises a row select transistor coupled in series with a source follower transistor, wherein the source follower transistor includes a polysilicon source follower gate comprising opaque silicide coupled to the node. 
     
     
         10 . The CMOS imager of  claim 8 , wherein the transfer gate and the reset gate further comprise a barrier metal portion. 
     
     
         11 . The CMOS imager of  claim 6 , wherein the silicide comprises a refractory metal. 
     
     
         12 . The CMOS imager of  claim 6 , wherein the transfer gate comprises a barrier metal layer. 
     
     
         13 . The CMOS imager of  claim 6 , wherein the photosensor is a photogate. 
     
     
         14 . The CMOS imager of  claim 7 , wherein the readout circuit is configured to provide correlated sampling of signals from the pixel. 
     
     
         15 . The CMOS imager of  claim 14 , wherein the silicide comprises a refractory metal. 
     
     
         16 . The CMOS imager of  claim 15 , further comprising an analog-to-digital converter for producing digital signals from analog signals from pixels of the array, and image processing circuitry for processing said digital signals. 
     
     
         17 . The CMOS imager of  claim 6 , further comprising a load transistor coupled to a ground source, wherein the at least one pixel further comprises a source follower transistor coupled in series with the load transistor, wherein the source follower transistor includes a polysilicon source follower gate comprising opaque silicide coupled to the node. 
     
     
         18 . A CMOS imager, comprising:
 a pixel array comprising a plurality of photosensors to accumulate photogenerated charges and a plurality of reset transistors each having a reset gate, each reset transistor capable of resetting a corresponding one of the photosensors, wherein the reset gates include a conductive layer comprising a refractory metal, and wherein the regions above the photosensors and above the sources and drains of the reset transistors are free of the conductive layer;   timing and control circuitry to read out pixels of the array; and   an analog-to-digital converter coupled to receive signals from pixels of the array.   
     
     
         19 . The CMOS imager of  claim 18 , wherein the pixel array further comprises a plurality of transfer gates to transfer charges from the photosensors, wherein the transfer gates include the conductive layer comprising the refractory metal. 
     
     
         20 . The CMOS imager of  claim 19 , wherein the pixel array further comprises a plurality of row select and source follower transistors coupled in series, wherein the source follower transistors include the conductive layer comprising the refractory metal. 
     
     
         21 . The CMOS imager of  claim 19 , wherein the reset gates and the transfer gates further comprise a barrier metal layer. 
     
     
         22 . The CMOS imager of  claim 18 , wherein the reset gates further include a barrier metal layer. 
     
     
         23 . The CMOS imager of  claim 18 , wherein the photosensors are photogates. 
     
     
         24 . The CMOS imager of  claim 18 , further comprising an analog-to-digital converter for producing digital signals from analog signals from pixels of the array, and image processing circuitry for processing said digital signals. 
     
     
         25 . The CMOS imager of  claim 24 , further comprising a plurality of load transistors and source follower transistors coupled in series, wherein the source follower transistors include the conductive layer comprising the refractory metal. 
     
     
         26 . The CMOS imager of  claim 18 , further comprising a plurality of load transistors and source follower transistors coupled in series, wherein the source follower transistors include the conductive layer comprising the refractory metal. 
     
     
         27 . An apparatus, comprising:
 a pixel array, each pixel of the array comprising at least one silicided transistor gate, at least one transistor source/drain that is not silicided, and at least one photosensor that is not silicided to prevent light blockage;   a readout circuit configured to provide correlated sampling of each pixel of the array; and   an analog-to-digital converter coupled to receive signals from pixels of the array.   
     
     
         28 . The apparatus of  claim 27 , wherein each pixel of the array further comprises a plurality of silicided transistor gates. 
     
     
         29 . The apparatus of  claim 28 , wherein the silicided transistor gates include a refractory metal. 
     
     
         30 . The apparatus of  claim 29 , wherein the silicided transistor gates further include a barrier metal layer. 
     
     
         31 . The apparatus of  claim 27 , wherein the silicided transistor gate further includes a barrier metal layer. 
     
     
         32 . The apparatus of  claim 27 , wherein the photosensor is a photogate. 
     
     
         33 . The apparatus of  claim 27 , further comprising image processing circuitry for processing signals derived from the pixel array. 
     
     
         34 . The apparatus of  claim 27 , wherein the transistor gate is a transfer transistor gate. 
     
     
         35 . The apparatus of  claim 27 , wherein the transistor gate is a reset transistor gate. 
     
     
         36 . A camera system, comprising:
 a processor;   random access memory coupled to the processor;   a non-volatile memory subsystem coupled to the processor and configured to enable use of removable storage media; and   a CMOS imager, coupled to the processor, comprising a pixel array having silicided gates of transistors, unsilicided source/drain regions of the transistors, and an analog-to-digital converter.   
     
     
         37 . The system of  claim 36 , wherein the silicided transistors include a plurality of silicided transfer transistors and the CMOS imager further comprises a readout circuit configured to provide correlated sampling. 
     
     
         38 . The system of  claim 37 , wherein the silicided transistors include a refractory metal. 
     
     
         39 . The system of  claim 38 , wherein the silicided transistors include a barrier metal layer. 
     
     
         40 . The system of  claim 36 , wherein the silicided transistors include a refractory metal. 
     
     
         41 . The system of  claim 36 , wherein the CMOS imager further comprises image processing circuitry for processing signals derived from the pixel array. 
     
     
         42 . The system of  claim 41 , wherein the removable storage media includes optical storage media. 
     
     
         43 . The system of  claim 42 , wherein the silicided transistors include a plurality of silicided transfer transistors and the CMOS imager further comprises a readout circuit configured to provide processing circuitry for processing signals derived from said readout circuit.