Performing Data Operations Using Non Volatile Third Dimension Memory

Abstract

Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.

What is claimed is: 
     
         1 . An integrated circuit (IC) for replacing at least one hard disk drive, comprising:
 a silicon die including fabricated thereon
 a bus, 
 a processor configured to execute instructions stored in a computer readable medium, the processor electrically coupled with the bus, and 
 a communications interface electrically coupled with the bus, 
   the silicon die further including integrally fabricated directly above and in contact with the silicon die
 a plurality of non-volatile two-terminal memory arrays in electrical communication with the bus, each array including a plurality of two-terminal memory elements arranged in a cross-point array configuration and operative to store non-volatile data as a plurality of conductivity profiles that are retained in the absence of electrical power, each two-terminal memory element (ME) has exactly two terminals and includes a tunnel barrier layer having a first thickness less than 50 Å, the tunnel barrier layer is direct contact with an ion reservoir including mobile oxygen ions that are moveable between the tunnel barrier layer and the ion reservoir in response to a write voltage applied across the two-terminal memory element, 
   a first one of the plurality of non-volatile two-terminal memory arrays is configured as non-volatile system memory and stores data including the instructions for the processor,   a second one of the plurality of non-volatile two-terminal memory arrays is configured as a non-volatile storage device, and   a third one of the plurality of non-volatile two-terminal memory arrays is configured as a non-volatile storage medium operative to replace a hard disk drive (HDD),   the silicon die further including fabricated thereon
 access circuitry, and 
 disk controller circuitry, 
   the access circuitry configured to perform data operations on the non-volatile system memory and the non-volatile storage device, the disk controller circuitry is electrically coupled with the access circuitry and the non-volatile storage medium, the disk controller circuitry configured to perform access requests on the non-volatile storage medium in response to HDD commands electrically communicated on the bus, and   the non-volatile two-terminal memory arrays are electrically coupled with the access circuitry.   
     
     
         2 . The IC of  claim 1  and further comprising: an input/output (I/O) device in electrical communication with the bus. 
     
     
         3 . The IC of  claim 2 , wherein the I/O device is external to the silicon die. 
     
     
         4 . The IC of  claim 2 , wherein the I/O device is fabricated on the silicon die. 
     
     
         5 . The IC of  claim 1 , wherein the communications interface is electrically coupled with an external communication link. 
     
     
         6 . The IC of  claim 1 , wherein the HDD commands are electrically communicated on the bus by the processor, the communications interface, or both. 
     
     
         7 . The IC of  claim 1 , wherein an external communication link is electrically coupled with the communications interface, the external communication link electrically communicates the HDD commands to the communications interface, and the communications interface electrically communicates the HDD commands on the bus. 
     
     
         8 . The IC of  claim 1 , wherein the silicon die further includes circuitry configured to perform direct memory access (DMA) on at least one of the plurality of non-volatile two-terminal memory arrays. 
     
     
         9 . The IC of  claim 1 , wherein the non-volatile storage device is operative as a computer readable medium configured to store the instructions used by the processor, and at system power up, the access circuitry reads the instructions from the non-volatile storage device and writes the instructions to the non-volatile system memory. 
     
     
         10 . The IC of  claim 1 , wherein the plurality of non-volatile two-terminal memory arrays comprises a plurality of vertically stacked memory planes that are in contact with one another, are integrally fabricated directly above the silicon die, and are electrically coupled with the access circuitry, each memory plane includes at least one of the plurality of non-volatile two-terminal memory arrays. 
     
     
         11 . The IC of  claim 1 , wherein the access request comprises a read operation to the non-volatile storage medium. 
     
     
         12 . The IC of  claim 1 , wherein the access request comprises a write operation to the non-volatile storage medium. 
     
     
         13 . The IC of  claim 1 , wherein at least a portion of the non-volatile system memory is operative to store non-volatile access data for the access request on the non-volatile storage medium, and the non-volatile access data comprises one or more types of data selected from the group consisting of a file allocation table (FAT), a disk drive directory, a pointer, a disk drive map, a cylinder cache table, and cylinder-head-sector (CHS). 
     
     
         14 . The IC of  claim 1 , wherein the plurality of conductivity profiles are indicative of multi-level data operative to store more than one bit of non-volatile data that is retained in the absence of electrical power. 
     
     
         15 . The IC of  claim 1 , wherein the non-volatile storage device is configured as a read only memory (ROM). 
     
     
         15 . The IC of  claim 1 , wherein the ion reservoir comprises a layer of a conductive metal oxide (CMO). 
     
     
         16 . The IC of  claim 15 , wherein the CMO comprises a perovskite. 
     
     
         17 . The IC of  claim 1 , wherein the first thickness of the tunnel barrier layer is configured for electron tunneling when a data operations voltage is applied across the two terminals of the ME. 
     
     
         18 . The IC of  claim 1 , wherein the tunnel barrier layer comprises an electrolytic tunnel barrier layer. 
     
     
         19 . The IC of  claim 18 , wherein the electrolytic tunnel barrier layer is an electrolyte for the mobile oxygen ions and is permeable by the mobile oxygen ions only when the write voltage is applied across the two-terminals of the ME. 
     
     
         20 . The IC of  claim 1 , wherein the ion reservoir comprises a mixed valence conductive oxide