Methods of manufacturing a memory device having a carbon nanotube

Abstract

A method of manufacturing a memory device having a carbon nanotube can be provided by forming a lower electrode on a substrate and forming an insulating interlayer on the lower electrode. An upper electrode including a diode can be formed on the insulating interlayer, where the upper electrode can have a first void exposing a sidewall of the diode and a portion of the insulating interlayer. A portion of the insulating interlayer can be partially removed to form an insulating interlayer pattern having a second void that exposes a portion of the lower electrode, where the second void can be connected with the first void. A carbon nanotube wiring can be formed from the lower electrode through the second and first voids, where the carbon nanotube wiring may be capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode.

What is claimed is: 
     
         1 . A method of manufacturing a memory device having a carbon nanotube, comprising:
 forming a lower electrode on a substrate;   forming an insulating interlayer on the lower electrode;   forming an upper electrode including a diode on the insulating interlayer, the upper electrode having a first void exposing a sidewall of the diode and a portion of the insulating interlayer;   partially removing a portion of the insulating interlayer to form an insulating interlayer pattern having a second void that exposes a portion of the lower electrode, the second void being connected with the first void; and   forming a carbon nanotube wiring from the lower electrode through the second void and the first void, the carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode.   
     
     
         2 . The method of  claim 1 , wherein forming the upper electrode having the diode comprises:
 forming an n-type polysilicon pattern on the insulating interlayer to have a third void exposing a portion of the insulating interlayer, the third void having a dimension larger than that of the first void; and   forming a p-type polysilicon pattern on a sidewall of the n-type polysilicon pattern exposed by the third void.   
     
     
         3 . The method of  claim 1 , wherein forming the upper electrode having the diode comprises:
 forming a metal layer pattern on the insulating interlayer to have a fourth void exposing a portion of the insulating interlayer, the fourth void having a dimension larger than that of the first void;   forming an n-type polysilicon pattern on a sidewall of the metal layer pattern exposed by the fourth void, the n-type polysilicon pattern including a third void having a dimension larger than that of the first void; and   forming a p-type polysilicon pattern on a sidewall of the n-type polysilicon pattern exposed by the third void.   
     
     
         4 . The method of  claim 1 , wherein forming the insulating interlayer pattern having the second void comprises:
 forming a mask spacer along a sidewall of the upper electrode exposed by the first void;   drying etching an exposed portion of the insulating interlayer to form the insulating interlayer pattern having the second void that exposes a portion of the lower electrode, the second void having a dimension smaller than that of the first void; and   removing the mask spacer from the sidewall of the upper electrode.   
     
     
         5 . The method of  claim 1 , wherein forming the carbon nanotube wiring comprises:
 growing at least one carbon nanotube from a surface of the lower electrode exposed by the second void toward the upper electrode.   
     
     
         6 . The method of  claim 1 , further comprising:
 forming a contact metal layer on the lower electrode; and   forming a catalyst layer on the contact metal layer.   
     
     
         7 . The method of  claim 1 , further comprising forming an upper insulation layer on the upper electrode and the carbon nanotube wiring.