Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation

Abstract

A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.

What is claimed is: 
     
         1 . A method for associating one or more memory buffers in a computing system with a plurality of memory channels, the method comprising:
 associating a first memory buffer and a first sequence identifier to a first plurality of memory banks, wherein the first plurality of memory banks spans over a first set of one or more memory channels;   associating a second memory buffer and a second sequence identifier to a second plurality of memory banks, wherein the second plurality of memory banks spans over a second set of one or more memory channels; and   accessing the first and second memory buffers based on the first and second sequence identifiers.   
     
     
         2 . The method of  claim 1 , further comprising:
 executing a first memory operation associated with the first memory buffer at a first operating frequency;   executing a second memory operation associated with the second memory buffer at a second operating frequency, wherein the first operating frequency is different from the second operating frequency; and   de-allocating the first and second memory buffers from their respective first and second plurality of memory banks, after the execution of the first and second memory operations, respectively.   
     
     
         3 . The method of  claim 1 , wherein the associating the first memory buffer comprises allocating the first memory buffer to the first plurality of memory banks. 
     
     
         4 . The method of  claim 1 , wherein the associating the second memory buffer comprises allocating the second memory buffer to the second plurality of memory banks, the second plurality of memory banks being different from the first plurality of memory banks. 
     
     
         5 . The method of  claim 1 , wherein the associating the second memory buffer comprises allocating the second memory buffer to the second plurality of memory banks, the second plurality of memory banks being the same as the first plurality of memory banks. 
     
     
         6 . The method of  claim 1 , wherein the accessing the first and second memory buffers comprises accessing the first and second memory buffers in sequence to avoid memory bank contention and to utilize a full bandwidth of the plurality of memory channels. 
     
     
         7 . A computer program product comprising a computer-usable medium having computer program logic recorded thereon that, when executed by one or more processors, associates one or more memory buffers in a computing system with a plurality of memory channels, the computer program logic comprising:
 first computer readable program code that enables a processor to associate a first memory buffer and a first sequence identifier to a first plurality of memory banks, wherein the first plurality of memory banks spans over a first set of one or more memory channels;   second computer readable program code that enables a processor to associate a second memory buffer and a second sequence identifier to a second plurality of memory banks, wherein the second plurality of memory banks spans over a second set of one or more memory channels; and   third computer readable program code that enables a processor to access the first and second memory buffers based on the first and second sequence identifiers.   
     
     
         8 . The computer program product of  claim 7 , wherein the computer program logic further comprises:
 fourth computer readable program code that enables a processor to execute a first memory operation associated with the first memory buffer at a first operating frequency;   fifth computer readable program code that enables a processor to execute a second memory operation associated with the second memory buffer at a second operating frequency, wherein the first operating frequency is different from the second operating frequency; and   sixth computer readable program code that enables a processor to de-allocate the first and second memory buffers from their respective first and second plurality of memory banks, after the execution of the first and second memory operations, respectively.   
     
     
         9 . The computer program product of  claim 7 , wherein the first computer readable program code comprises:
 fourth computer readable program code that enables a processor to allocate the first memory buffer to the first plurality of memory banks.   
     
     
         10 . The computer program product of  claim 7 , wherein the second computer readable program code comprises:
 fourth computer readable program code that enables a processor to allocate the second memory buffer to the second plurality of memory banks, the second plurality of memory banks being different from the first plurality of memory banks.   
     
     
         11 . The computer program product of  claim 7 , wherein the second computer readable program code comprises:
 fourth computer readable program code that enables a processor to allocate the second memory buffer to the second plurality of memory banks, the second plurality of memory banks being the same as the first plurality of memory banks.   
     
     
         12 . The computer program product of  claim 7 , wherein the third computer readable program code comprises:
 fourth computer readable program code that enables a processor to access the first and second memory buffers in sequence to avoid memory bank contention and to utilize a full bandwidth of the plurality of memory channels.   
     
     
         13 . A computing system, comprising:
 a first client device;   a second client device;   a plurality of memory channels, wherein the plurality of memory channels comprises a respective plurality of memory devices; and   a memory controller configured to communicatively couple the first and second client devices to the plurality of memory channels and configured to:
 allocate a first memory buffer and a first sequence identifier to a first plurality of memory banks, wherein the first plurality of memory banks spans over a first set of one or more memory channels; 
 allocate a second memory buffer and a second sequence identifier to a second plurality of memory banks, wherein the second plurality of memory banks spans over a second set of one or more memory channels; and 
 access the first and second memory buffers based on the first and second sequence identifiers. 
   
     
     
         14 . The computing system of  claim 13 , further comprising:
 a plurality of data buses that correspond to the plurality of memory devices, wherein the plurality of data buses is configured to transfer data between the memory controller and the respective plurality of memory devices.   
     
     
         15 . The computing system of  claim 14 , wherein the memory controller is configured to control a transfer of data between the first client device, or the second client device, and the plurality of memory devices using an entire bandwidth of the plurality of data buses. 
     
     
         16 . The computing system of  claim 13 , wherein the first and second client devices comprise at least one of a central processing unit, a graphics processing unit, and an application-specific integrated circuit. 
     
     
         17 . The computing system of  claim 13 , wherein each of the plurality of memory devices comprises a Dynamic Random Access Memory (DRAM) device. 
     
     
         18 . The computing system of  claim 13 , wherein the memory controller is configured to:
 execute a first memory operation associated with the first memory buffer at a first operating frequency;   execute a second memory operation associated with the second memory buffer at a second operating frequency, wherein the first operating frequency is different from the second operating frequency; and   de-allocate the first and second memory buffers from their respective first and second plurality of memory banks, after the execution of the first and second memory operations, respectively.   
     
     
         19 . The computing system of  claim 13 , wherein the memory controller is configured to allocate the second memory buffer to the second plurality of memory banks, the second plurality of memory banks being different from the first plurality of memory banks. 
     
     
         20 . The computing system of  claim 13 , wherein the memory controller is configured to allocate the second memory buffer to the second plurality of memory banks, the second plurality of memory banks being the same as the first plurality of memory banks. 
     
     
         21 . The computing system of  claim 13 , wherein the memory controller is configured to access the first and second memory buffers in sequence to avoid memory bank contention and to utilize a full bandwidth of the plurality of memory channels. 
     
     
         22 . The computing system of  claim 13 , wherein the memory controller is configured to associate the first memory buffer and the second memory buffer to the first plurality of memory banks and to the second plurality of memory banks, respectively.