Semiconductor package and method for making the same

Abstract

A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a semiconductor substrate having front and rear sides, two opposite lateral sides transverse to said front and rear sides, a pad-mounting face disposed at said front side, and at least one bonding pad formed on said pad-mounting face;   a first inner insulator layer formed on said pad-mounting face and formed with at least one pad-aligned hole that exposes said bonding pad;   at least one internal wiring connected to said bonding pad, extending therefrom through said pad-aligned hole to said front side of said semiconductor substrate, and further extending from said front side of said semiconductor substrate along one of said lateral sides of said semiconductor substrate to said rear side of said semiconductor substrate, said internal wiring including a first segment formed on said first inner insulator layer, a second segment disposed at said one of said lateral sides of said semiconductor substrate, and a third segment disposed at said rear side of said semiconductor substrate;   a first outer insulator layer disposed at said front side of said semiconductor substrate and having a portion that is formed on said first segment of said internal wiring and that is formed with at least one first wire-connecting hole which exposes a portion of said first segment of said internal wiring;   a second outer insulator layer disposed at said rear side of said semiconductor substrate and having a portion that is formed on said third segment of said internal wiring and that is formed with at least one second wire-connecting hole which exposes a portion of said third segment of said internal wiring;   a second inner insulator layer; and   two opposite side insulator layers;   wherein said semiconductor substrate further has a rear face disposed at said rear side of said semiconductor substrate, and two opposite side faces disposed at said lateral sides, respectively, and interconnects said pad-mounting face and said rear face, said second inner insulator layer being formed on said rear face of said semiconductor substrate, said side insulator layers being formed on said side faces of said semiconductor substrate, respectively, said second segment of said internal wiring being formed on one of said side insulator layers that is disposed at said one of said lateral sides of said semiconductor substrate, said third segment of said internal wiring being formed on said second inner insulator layer.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising first and second wire-defining layers, said first wire-defining layer being formed on said first inner insulator layer and being formed with at least one first wire-defining hole that exposes a portion of said first inner insulator layer, said first segment of said internal wiring extending into and through said first wire-defining hole in said first wire-defining layer and being formed on said portion of said first inner insulator layer exposed by said first wire-defining hole, said second wire-defining layer being formed on said second inner insulator layer and being formed with at least one second wire-defining hole that exposes a portion of said second inner insulator layer, said third segment of said internal wiring extending into and through said second wire-defining hole in said second wire-defining layer and being formed on said portion of said second inner insulator layer exposed by said second wire-defining hole, said first outer insulator layer further having another portion that is formed on said first wire-defining layer, said second outer insulator layer further having another portion that is formed on said second wire-defining layer. 
     
     
         3 . A method for making semiconductor packages, comprising:
 forming a plurality of upper recesses in a semiconductor substrate such that each of the upper recesses extends through a pad-mounting face of the semiconductor substrate and is disposed at a respective one of cutting lines of the semiconductor substrate;   forming a first inner insulator layer on the pad-mounting face of the semiconductor substrate such that the first inner insulator layer fills the upper recesses;   forming a plurality of pad-aligned holes in the first inner insulator layer such that the pad-aligned holes expose bonding pads on the pad-mounting face of the semiconductor substrate, respectively, and a plurality of upper side holes in the first inner insulator layer such that the upper side holes are disposed respectively at the cutting lines of the semiconductor substrate, each of the upper side holes being defined by a hole-defining wall that extends into a respective one of the upper recesses;   forming a first wire-defining layer on the first inner insulator layer;   forming a plurality of first wire-defining holes in the first wire-defining layer such that each of the first wire-defining holes extends between and communicates spatially with a respective one of the pad-aligned holes and a respective one of the upper side holes;   forming a plurality of first conductive traces such that each of the first conductive traces fills a respective one of the pad-aligned holes to connect with a respective one of the bonding pads, and further fills a respective one of the first wire-defining holes and a respective one of the upper side holes;   forming a plurality of lower recesses in the semiconductor substrate such that each of the lower recesses extends through a rear face of the semiconductor substrate opposite to the pad-mounting face and communicates spatially with a respective one of the upper recesses;   forming a second inner insulator layer on the rear face of the semiconductor substrate such that the second inner insulator layer fills the lower recesses;   forming a plurality of lower side holes in the second inner insulator layer such that the lower side holes are disposed respectively at the cutting lines of the semiconductor substrate, each of the lower side holes communicating spatially with a respective one of the upper side holes and being defined by a hole-defining wall that extends into a respective one of the lower recesses;   forming a second wire-defining layer on the second inner insulator layer;   forming a plurality of second wire-defining holes in the second wire-defining layer such that each of the second wire-defining holes communicates spatially with and is transverse to a respective one of the lower side holes;   forming a plurality of second conductive traces such that each of the second conductive traces fills a respective one of the second wire-defining holes and a respective one of the lower side holes to connect with a respective one of the first conductive traces;   forming a first outer insulator layer to cover the first wire-defining layer and the first conductive traces;   forming a plurality of wire-connecting holes in the first outer insulator layer to expose portions of the first conductive traces, respectively;   forming a second outer insulator layer to cover the second wire-defining layer and the second conductive traces;   forming a plurality of wire-connecting holes in the second outer insulator layer to expose portions of the second conductive traces, respectively;   forming a plurality of conductive posts such that each of the conductive posts fills a respective one of the wire-connecting holes in the first outer insulator layer to connect with a respective one of the first conductive traces and extends outwardly of the respective one of the wire-connecting holes in the first outer insulator layer; and   cutting an assembly of the first and second inner insulator layers, the first and second outer insulator layers, the first and second wire-defining layers, the first and second conductive traces, the conductive posts, and the semiconductor substrate along the cutting lines so as to form the semiconductor packages.   
     
     
         4 . The method of  claim 1 , further comprising forming a metal layer on each of the bonding pads prior to formation of the first wire-defining layer.