Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.

What is claimed is: 
     
         1 . A nonvolatile semiconductor memory device, comprising:
 a plurality of memory blocks, each including a plurality of cell units and each configured as a smallest unit of an erase operation;   a first line provided commonly to the plurality of memory blocks and connected to one ends of the plurality of cell units;   a second line connected to the other ends of the plurality of cell units; and   a control circuit configured to control a voltage applied to the plurality of memory blocks,   each of the plurality of cell units comprising:   a memory string configured by a plurality of memory transistors connected in series, the memory transistors being electrically rewritable;   a first transistor having one end connected to one end of the memory string;   a second transistor provided between the other end of the memory string and the second line; and   a diode provided between the first transistor and the first line and having a forward bias direction from a side of the first transistor to a side of the first line,   the memory string comprising:   a first semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate, the first semiconductor layer being configured to function as a body of the memory transistors;   a charge storage layer formed to surround a side surface of the columnar portion and configured to be capable of storing a charge; and   a first conductive layer formed commonly in the plurality of memory blocks to surround the side surface of the columnar portion with the charge storage layer interposed therebetween, the first conductive layer being configured to function as a gate of the memory transistors, and   the diode comprising:   a second semiconductor layer of a first conductivity type, the second semiconductor layer extending in the perpendicular direction with respect to the substrate; and   a third semiconductor layer of a second conductivity type, the third semiconductor layer being in contact with an upper surface of the second semiconductor layer and extending in the perpendicular direction with respect to the substrate,   the control circuit being configured to perform the erase operation in a selected one of the memory blocks by setting a voltage of the first line higher than a voltage of a gate of the first transistor by a first voltage to generate a GIDL current for raising a voltage of the body of the memory transistors, and setting a voltage of the gate of the memory transistors lower than the voltage of the body of the memory transistors by a second voltage, and   the control circuit being configured to prohibit the erase operation in an unselected one of the memory blocks by setting a voltage difference between the voltage of the first line and the voltage of the gate of the first transistor to a third voltage different from the first voltage for prohibiting generation of the GIDL current.   
     
     
         2 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the control circuit is configured to perform the erase operation in a selected one of the memory blocks by setting a voltage of the second line higher than a voltage of a gate of the second transistor by the first voltage to generate the GIDL current for raising a voltage of the body of the memory transistors, and setting a voltage of the gate of the memory transistors lower than the voltage of the body of the memory transistors by the second voltage, and   the control circuit is configured to prohibit the erase operation in an unselected one of the memory blocks by setting a voltage difference between the voltage of the second line and the voltage of the gate of the second transistor to the third voltage for prohibiting generation of the GIDL current.   
     
     
         3 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the second line is divided on a memory block basis, and   wherein the control circuit is configured to prohibit the erase operation in an unselected one of the memory blocks by setting the second transistor to an on-state.   
     
     
         4 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the control circuit is configured to perform a write operation for writing data to the memory transistors,   by executing   a first processing setting the second transistor included in a selected one of the cell units to an on-state, thereby a voltage of the body of the memory transistors included in the selected one of the cell units being set to not less than a voltage that may be applied to the first line during the write operation,   a second processing setting the first transistor included in the selected one of the cell units to an on-state after the first processing, and   a third processing setting the gate of the selected memory transistors to a fourth voltage.   
     
     
         5 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the control circuit is configured to perform a read operation for reading data from a selected memory transistor included in a selected one of the cell units,   by setting a voltage of the second line higher than the voltage of the first line by a fifth voltage, setting the first transistor and the second transistor included in the selected one of the cell units to an on-state, applying a sixth voltage to the gate of unselected memory transistors included in the selected one of the cell units, and applying a seventh voltage lower than the sixth voltage to the gate of the selected memory transistors.   
     
     
         6 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the diode further comprises an ohmic contact layer configured to be in contact with a lower surface of the second semiconductor layer.   
     
     
         7 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the diode further comprises a fourth semiconductor layer of the first conductivity type, the fourth semiconductor layer being in contact with an upper surface of the third semiconductor layer and extending in the perpendicular direction with respect to the substrate.   
     
     
         8 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the first semiconductor layer includes a joining portion configured to join lower ends of a pair of the columnar portions.   
     
     
         9 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the first transistor comprises:   a fifth semiconductor layer extending in the perpendicular direction with respect to the substrate and configured to function as a body of the first transistor;   a first gate insulating layer formed to surround a side surface of the fifth semiconductor layer; and   a second conductive layer formed to surround the side surface of the fifth semiconductor layer with the first gate insulating layer interposed therebetween, the second conductive layer being configured to function as the gate of the first transistor.   
     
     
         10 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the second transistor comprises:   a sixth semiconductor layer extending in the perpendicular direction with respect to the substrate and configured to function as a body of the second transistor;   a second gate insulating layer formed to surround a side surface of the sixth semiconductor layer; and   a third conductive layer formed to surround the side surface of the sixth semiconductor layer with the second gate insulating layer interposed therebetween, the third conductive layer being configured to function as the gate of the second transistor.   
     
     
         11 . The nonvolatile semiconductor memory device according to  claim 8 ,
 wherein the memory string further comprises:   a fourth conductive layer formed to surround a side surface of the joining portion with the charge storage layer interposed therebetween.   
     
     
         12 . A nonvolatile semiconductor memory device, comprising:
 a plurality of memory blocks, each configured as an arrangement of a plurality of cell units and each configured as a unit of execution of an erase operation, the erase operation being configured to erase data retained in the cell units;   a first line provided commonly to the plurality of memory blocks and connected to one ends of the plurality of cell units;   a second line connected to the other ends of the plurality of cell units; and   a control circuit configured to control a voltage applied to the plurality of memory blocks,   each of the plurality of cell units comprising:   a memory string configured by a plurality of memory transistors connected in series, the memory transistors being electrically rewritable;   a first transistor having one end connected to one end of the memory string;   a second transistor provided between the other end of the memory string and the second line; and   a diode provided between the first transistor and the first line and having a forward bias direction from a side of the first line to a side of the first transistor,   the memory string comprising:   a first semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate, the first semiconductor layer being configured to function as a body of the memory transistors;   a charge storage layer formed to surround a side surface of the columnar portion and configured to be capable of storing a charge; and   a first conductive layer formed commonly in the plurality of memory blocks to surround the side surface of the columnar portion with the charge storage layer interposed therebetween, the first conductive layer being configured to function as a gate of the memory transistors, and   the diode comprising:   a second semiconductor layer of a first conductivity type, the second semiconductor layer extending in the perpendicular direction with respect to the substrate; and   a third semiconductor layer of a second conductivity type, the third semiconductor layer being in contact with the second semiconductor layer and extending in the perpendicular direction with respect to the substrate,   the control circuit being configured to perform the erase operation in a selected one of the memory blocks by setting a voltage of the second line higher than a voltage of a gate of the second transistor by a first voltage to generate a GIDL current for raising a voltage of the body of the memory transistors, and setting a voltage of the gate of the memory transistors lower than the voltage of the body of the memory transistors by a second voltage, and   the control circuit being configured to prohibit the erase operation in an unselected one of the memory blocks by setting a voltage difference between the voltage of the second line and the voltage of the gate of the second transistor to a third voltage different from the first voltage for prohibiting generation of the GIDL current.   
     
     
         13 . The nonvolatile semiconductor memory device according to  claim 12 ,
 wherein the second line is divided on a memory block basis, and   wherein the control circuit is configured to prohibit the erase operation in an unselected one of the memory blocks by setting the second transistor to an on-state.   
     
     
         14 . The nonvolatile semiconductor memory device according to  claim 12 ,
 wherein the control circuit is configured to perform a write operation for writing data to the memory transistors,   by executing   a first processing setting the second transistor included in a selected one of the cell units to an on-state, thereby a voltage of the body of the memory transistors included in the selected one of the cell units being set to not less than a voltage that may be applied to the first line during the write operation,   a second processing setting the first transistor included in the selected one of the cell units to an on-state after the first processing, and   a third processing setting the gate of the selected memory transistors to a fourth voltage.   
     
     
         15 . The nonvolatile semiconductor memory device according to  claim 12 ,
 wherein the control circuit is configured to perform a read operation for reading data from a selected memory transistor included in a selected one of the cell units,   by setting a voltage of the second line higher than the voltage of the first line by a fifth voltage, setting the first transistor and the second transistor included in the selected one of the cell units to an on-state, applying a sixth voltage to the gate of unselected memory transistors included in the selected one of the cell units, and applying a seventh voltage lower than the sixth voltage to the gate of the selected memory transistors.   
     
     
         16 . The nonvolatile semiconductor memory device according to  claim 12 ,
 wherein the diode further comprises a fourth semiconductor layer of the first conductivity type, the fourth semiconductor layer being in contact with an upper surface of the third semiconductor layer and extending in the perpendicular direction with respect to the substrate.   
     
     
         17 . The nonvolatile semiconductor memory device according to  claim 12 ,
 wherein the first semiconductor layer has an upper portion configured by a semiconductor of the second conductivity type.   
     
     
         18 . The nonvolatile semiconductor memory device according to  claim 12 ,
 wherein the first semiconductor layer includes a joining portion configured to join lower ends of a pair of the columnar portions.   
     
     
         19 . The nonvolatile semiconductor memory device according to  claim 12 ,
 wherein the first transistor comprises:   a fifth semiconductor layer extending in the perpendicular direction with respect to the substrate and configured to function as a body of the first transistor;   a first gate insulating layer formed to surround a side surface of the fifth semiconductor layer; and   a second conductive layer formed to surround the side surface of the fifth semiconductor layer with the first gate insulating layer interposed therebetween, the second conductive layer being configured to function as the gate of the first transistor.   
     
     
         20 . The nonvolatile semiconductor memory device according to  claim 12 ,
 wherein the second transistor comprises:   a sixth semiconductor layer extending in the perpendicular direction with respect to the substrate and configured to function as a body of the second transistor;   a second gate insulating layer formed to surround a side surface of the sixth semiconductor layer; and   a third conductive layer formed to surround the side surface of the sixth semiconductor layer with the second gate insulating layer interposed therebetween, the third conductive layer being configured to function as the gate of the second transistor.