Error correction circuit and method, and semiconductor memory device including the circuit

Abstract

An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.

What is claimed is: 
     
         1 . An error correction method comprising:
 reading coded data;   generating a plurality of partial syndromes using the coded data;   calculating first error bit position data using a portion of the plurality of partial syndromes; and   calculating a plurality of bit position equation coefficients using the plurality of partial syndromes.   
     
     
         2 . The method of  claim 1 , wherein the calculating first error bit position data is performed at least partially concurrent with the calculating the plurality of bit position equation coefficients. 
     
     
         3 . The method of  claim 1 , further comprising determining whether an error type is a first error type or a second error type based on the plurality of bit position equation coefficients. 
     
     
         4 . The method of  claim 3  wherein the first error type is an error having a single bit error and the second error type is an error having multiple bit errors. 
     
     
         5 . The method of  claim 3  wherein the first error type is an error having two or fewer bit errors and the second error type is an error having three or more bit errors. 
     
     
         6 . The method of  claim 3 , wherein the number of errors of the second error type is greater than that of the first error type. 
     
     
         7 . The method of  claim 3  further comprising, if the error type is the first error type, correcting the coded data based on the first error position data. 
     
     
         8 . The method of  claim 3  further comprising, if the error type is the second error type, calculating second error bit position data based on the plurality of bit position equation coefficients. 
     
     
         9 . The method of  claim 8 , wherein a first calculation time required for a first error position detector to the first error bit position data is less than a second calculation time required for a second error position detector to calculate the second error bit position data 
     
     
         10 . The method of  claim 7  further comprising correcting the coded data based on the second error bit position data. 
     
     
         11 . An error correction method comprising:
 reading coded data;   generating a plurality of partial syndromes using the coded data; S 620     detecting a first error position using a portion of the plurality of partial syndromes;   generating a corresponding plurality of coefficients using the plurality of partial syndromes;   determining in relation to the plurality of coefficients whether the coded data includes less than or equal to a number of errors, or more than the number of errors;   correcting a first error using the detected first error position when the coded data includes less than or equal to the number of errors; and   detecting a second error position using the plurality of coefficients and correcting the second error using the detected second error position when the coded data includes more than the number of errors.