US2012074473A1PendingUtilityA1
Semiconductor Device
Est. expiryJul 29, 2028(~2 yrs left)· nominal 20-yr term from priority
Inventors:Sang Don Lee
H10D 30/62H10D 30/024H10B 12/056H10B 12/34H10B 12/36H10B 12/485H10B 12/053H10B 12/0335
46
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Claims
Abstract
A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate.
Claims
exact text as granted — not AI-modified1 . A semiconductor device, comprising:
a partial-insulated substrate comprising a connection region configured to couple an upper silicon layer to a lower semiconductor substrate and an insulating region configured to electrically disconnect the upper silicon layer from the lower semiconductor substrate; a channel region and a source/drain region over the insulating region; and a gate electrode on the channel region.
2 . The semiconductor device according to claim 1 , wherein the connection region is located below a partial portion of the channel region and a bit line contact region.
3 . The semiconductor device according to claim 2 , wherein the bit line contact region comprises an area between fin regions of neighboring cell transistors formed in an active region.
4 . The semiconductor device according to claim 1 , wherein the connection region is located below a partial portion of the channel region and a storage node contact region.
5 . The semiconductor device according to claim 4 , wherein the storage node contact region comprises areas outside fin regions of neighboring cell transistors formed in an active region.
6 . The semiconductor device according to claim 1 , wherein the insulating region is located below the channel region, a bit line contact region, and a partial portion of a storage node contact.
7 . The semiconductor device according to claim 11 , further comprising:
a gate oxide layer between the channel region and the gate electrode; and a spacer at sidewalls of the gate electrode.Cited by (0)
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