Memory reduced h264/mpeg-4 avc codec

Abstract

A method for reducing memory utilization in a digital video codec. The method generally includes the steps of (A) generating a second reference picture by downsampling a first reference picture using a pattern, wherein the pattern (i) comprises a two-dimensional grid and (ii) is unachievable by performing a vertical downsampling and separately performing a horizontal downsampling, (B) generating a third reference picture by upsampling the second reference picture and (C) processing an image in a video signal using the third reference picture.

1 . A method for reducing memory utilization in a digital video codec, comprising the steps of
 (A) generating a second picture by downsampling a first picture using a pattern, wherein said pattern is unachievable by performing a vertical downsampling and separately performing a horizontal downsampling;   (B) generating a third picture by upsampling said second picture; and   (C) decoding a fourth picture by inter-predicting from said third picture.   
     
     
         2 . The method according to  claim 1 , wherein said pattern comprises a quincunx pattern. 
     
     
         3 . The method according to  claim 1 , wherein said upsampling comprises (i) a first stage a four-neighbor, four-point median upsampling and (ii) a second stage two-neighbor, three-point median upsampling. 
     
     
         4 . The method according to  claim 1 , wherein said upsampling comprises a nonlinear interpolation. 
     
     
         5 . The method according to  claim 1 , wherein said digital video codec is compliant with at least one of (i) an H.264 recommendation and (ii) an MPEG-4/Advanced Video Coding recommendation. 
     
     
         6 . The method according to  claim 1 , wherein said downsampling is applied to a luminance channel and two chrominance channels of said first picture. 
     
     
         7 . A method for reducing memory utilization in a digital video codec, comprising the steps of:
 (A) generating a second picture by downsampling a first picture;   (B) generating a third picture by upsampling said second picture, wherein said upsampling comprises a nonlinear interpolation; and   (C) decoding a fourth picture by inter-predicting from said third picture.   
     
     
         8 . The method according to  claim 7 , wherein said nonlinear interpolation comprises a two-stage interpolation. 
     
     
         9 . The method according to  claim 7 , wherein said nonlinear interpolation comprises (i) a first stage a four-neighbor, four-point median upsampling and (ii) a second stage two-neighbor, three-point median upsampling. 
     
     
         10 . The method according to  claim 7 , wherein said downsampling comprises a quincunx downsampling. 
     
     
         11 . A system comprising:
 a circuit configured to (i) generate a second picture by downsampling a first picture using a pattern, wherein said pattern is unachievable by performing a vertical downsampling and separately performing a horizontal downsampling, (ii) generate a third picture by upsampling said second picture and (iii) decode a fourth picture by inter-predicting from said third picture; and   a memory configured to buffer said second picture.   
     
     
         12 . The system according to  claim 11 , wherein (i) said pattern comprises a quincunx pattern and (ii) said upsampling comprises a nonlinear interpolation. 
     
     
         13 . The system according to  claim 11 , wherein said circuit comprises a memory controller configured to (i) downsample a particular picture in a quincunx pattern and (ii) transfer said particular picture to said memory. 
     
     
         14 . The system according to  claim 11 , wherein said circuit comprises a memory controller configured to (i) receive a particular picture from said memory and (ii) upsample said particular picture with a nonlinear interpolation. 
     
     
         15 . The system according to  claim 11 , wherein said upsampling comprises (i) a first stage a four-neighbor, four-point median upsampling and (ii) a second stage two-neighbor, three-point median upsampling. 
     
     
         16 . A system comprising:
 a circuit configured to (i) generate a second picture by downsampling a first picture using a quincunx pattern, (ii) generate a third picture by upsampling said second picture using a nonlinear interpolation and (iii) decode a fourth picture by inter-prediction from said third picture; and   a first memory configured to buffer said second picture.   
     
     
         17 . The system according to  claim 16 , wherein said circuit is further configured to control buffering of a plurality of fifth pictures in a second memory. 
     
     
         18 . The system according to  claim 17 , wherein (i) said circuit and said first memory are formed on a first chip and (ii) said second memory is formed on a second chip. 
     
     
         19 . The system according to  claim 17 , wherein said second memory is configured to (i) downsample said fifth pictures received from said circuit using said quincunx pattern and (ii) upsample said fifth pictures prior to transmission to said circuit using said nonlinear interpolation. 
     
     
         20 . The system according to  claim 16 , wherein said nonlinear interpolation comprises (i) a first stage a four-neighbor, four-point median upsampling and (ii) a second stage two-neighbor, three-point median upsampling.