Method of manufacturing high-integrated semiconductor device and semiconductor device manufactured using the same

Abstract

A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a channel region having a pillar form, and a bit line comprising a metal layer to connect the plurality of vertical transistors.

1 . A method for manufacturing a semiconductor memory device, the method comprising:
 providing a pillar on a semiconductor substrate;   forming a barrier metal layer on the substrate and at a lower side of the pillar, the barrier metal layer being part of a bit line; and   forming a gate electrode on a sidewall of the pillar.   
     
     
         2 . The method according to  claim 1 , further comprising:
 etching the substrate to form a silicon line pattern in a first direction at a second lower side of the pillar;   forming a metal layer in the silicon line pattern;   forming a first insulating layer on the metal layer; and   isotropically etching the silicon line pattern in a second direction to cross the first direction,   wherein the metal layer and the barrier metal layer define the bit line.   
     
     
         3 . The method according to  claim 2 , further comprising:
 forming a mask layer over the semiconductor substrate and patterning the mask layer;   forming a first pattern by etching the semiconductor substrate using the patterned mask layer;   forming a spacer on a sidewall of the first pattern; and   etching the semiconductor substrate using the patterned mask layer and the spacer as an etch mask.   
     
     
         4 . The method according to  claim 3 , further comprising:
 forming a pad oxide layer on the semiconductor substrate;   forming a hard mask layer on the pad oxide layer;   coating a photoresist layer on the hard mask layer and patterning the photoresist layer;   etching an exposed hard mask layer using the patterned photoresist layer as an etch mask; and   etching the exposed pad oxide layer using the etched hard mask layer.   
     
     
         5 . The method according to  claim 2 , further comprising:
 forming a mask layer on the first insulating layer and patterning the mask layer having a line form along the second direction is that intersects the first direction;   forming a second pattern by etching the first insulating layer and the semiconductor substrate using the patterned mask layer; and   forming a spacer on a sidewall of the second pattern and isotropically etching the semiconductor substrate using the patterned mask layer and the spacer as an etch mask.   
     
     
         6 . The method according to  claim 2 , further comprising:
 depositing a barrier metal layer on an entire surface of a structure, including the pillar;   removing an exposed barrier metal layer by etching back the barrier metal layer;   sintering the barrier metal layer coming into contact with the semiconductor substrate by performing annealing;   etching the semiconductor substrate to a certain depth below the pillar;   removing the spacer; and   forming an insulating layer between the pillar, including the etched spacer, thereby insulating the metal layer and the barrier metal layer from each other at a given location.