Methods and Apparatuses for Circuit Simulation

Abstract

In one embodiment, a method comprising identifying a sub-network of the linear circuit, the sub-network having one or more internal nodes, one or more interface nodes, and branches connecting the one or more internal nodes and the one or more interface nodes, the sub-network having at least one of a capacitor and an inductor, is described. The method in one embodiment comprises determining a linear equation system for transient simulation of the linear circuit, the linear equation system containing no variable representing the one or more internal nodes.

1 . A non-transitory machine readable medium containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method of transient simulation of a linear circuit, comprising:
 identifying a sub-network of the linear circuit, the sub-network having one or more internal nodes, one or more interface nodes, and branches connecting the one or more internal nodes and the one or more interface nodes, the sub-network having at least one of a capacitor and an inductor; and   determining a linear equation system for transient simulation of the linear circuit, the linear equation system containing no variable representing the one or more internal nodes.   
     
     
         2 . The machine-readable medium of  claim 1 , wherein the sub-network has at least one branch connecting to a known voltage through one of a capacitor and an inductor. 
     
     
         3 . The machine-readable of  claim 1 , wherein the sub-network has no more than two interface nodes that have unknown voltages. 
     
     
         4 . The machine-readable of  claim 1 , further comprising:
 determining a representation of voltages at the one or more internal nodes of the sub-network from a representation of voltages at the one or more interface nodes.   
     
     
         5 . A method of transient simulation of a linear circuit, the method comprising:
 identifying a sub-network of the linear circuit, the sub-network having one or more internal nodes, one or more interface nodes, and branches connecting the one or more internal nodes and the one or more interface nodes, the sub-network having at least one of a capacitor and an inductor; and   determining a linear equation system for transient simulation of the linear circuit, the linear equation system containing no variable representing the one or more internal nodes.   
     
     
         6 . The method of  claim 5 , wherein the sub-network has at least one branch connecting to a known voltage through one of a capacitor and an inductor. 
     
     
         7 . The method of  claim 5 , wherein the sub-network has no more than two interface nodes that have unknown voltages. 
     
     
         8 . The method of  claim 5 , further comprising:
 determining a representation of voltages at the one or more internal nodes of the sub-network from a representation of voltages at the one or more interface nodes.   
     
     
         9 . A data processing system for transient simulation of a linear circuit, the data processing system comprising:
 means for identifying a sub-network of the linear circuit, the sub-network having one or more internal nodes, one or more interface nodes, and branches connecting the one or more internal nodes and the one or more interface nodes, the sub-network having at least one of a capacitor and an inductor; and   means for determining a linear equation system for transient simulation of the linear circuit, the linear equation system containing no variable representing the one or more internal nodes.   
     
     
         10 . The data processing system of  claim 9 , wherein the sub-network has at least one branch connecting to a known voltage through one of a capacitor and an inductor. 
     
     
         11 . The data processing system of  claim 9 , wherein the sub-network has no more than two interface nodes that have unknown voltages. 
     
     
         12 . The data processing system of  claim 9 , further comprising:
 means for determining a representation of voltages at the one or more internal nodes of the sub-network from a representation of voltages at the one or more interface nodes.