Three-dimensional semiconductor memory device and related method of manufacture

Abstract

A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

1 - 10 . (canceled) 
     
     
         11 . A three-dimensional semiconductor memory device, comprising:
 a substrate in which a penetration dent is formed;   an electrode structure disposed on the substrate and comprising sequentially stacked electrodes;   a vertical insulation layer penetrating the electrode structure and covering an inner wall of the penetration dent;   a semiconductor pattern penetrating the vertical insulation layer and inserted into the substrate; and   an oxide layer covering a sidewall of the penetration dent between the substrate and the electrode structure.   
     
     
         12 . The three-dimensional semiconductor memory device of  claim 11 , wherein the vertical insulation layer comprises an upper region in contact with a sidewall of the electrode structure and a lower region in contact with the sidewall of the penetration dent,
 wherein the oxide layer is in contact with the lower region of the vertical insulation layer.   
     
     
         13 . The three-dimensional semiconductor memory device of  claim 11 , wherein a distance between a top surface of the substrate and a bottom surface of a lowermost electrode is greater than a distance between a sidewall of the lowermost electrode and a sidewall of the semiconductor pattern. 
     
     
         14 . The three-dimensional semiconductor memory device of  claim 11 , wherein a vertical thickness of the oxide layer increases as the oxide layer is closer to the semiconductor pattern. 
     
     
         15 . The three-dimensional semiconductor memory device of  claim 11 , wherein the substrate comprises a rounded corner between the sidewall of the penetration dent and a top surface of the substrate. 
     
     
         16 . A three-dimensional semiconductor memory device, comprising:
 a substrate having a penetration dent and a plurality of impurity regions;   an electrode structure formed on a substrate and comprising a plurality of sequentially stacked electrodes;   a vertical insulation layer penetrating the electrode structure and covering an inner wall of the penetration dent to define a cylindrical boundary;   a semiconductor body formed within the cylindrical boundary of the vertical insulation layer and entering the penetration dent;   a semiconductor spacer formed between the semiconductor body and the vertical insulation layer; and   an oxide layer covering sidewalls of the penetration dent between the semiconductor body and the impurity regions.   
     
     
         17 . The three-dimensional semiconductor memory device of  claim 16 , further comprising an upper interconnection formed over the electrode structure and electrically connected to the semiconductor spacer. 
     
     
         18 . The three-dimensional semiconductor memory device of  claim 17 , wherein the upper interconnection forms a bitline connected to a cell string of a NAND flash memory. 
     
     
         19 . The three-dimensional semiconductor memory device of  claim 16 , wherein the oxide layer has curved edges. 
     
     
         20 . The three-dimensional semiconductor memory device of  claim 16 , wherein the semiconductor body and the semiconductor spacer comprise doped impurity regions.