Compensation of phase lock loop (pll) phase distribution caused by power amplifier ramping

Abstract

Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

1 . A method comprising:
 determining a power state of a power amplifier to receive an output signal of a phase lock loop;   enabling the phase lock loop in first mode when the power state of the power amplifier is constant; and   enabling the phase lock loop in second mode when the power state of the power amplifier is ramping.   
     
     
         2 . The method of  claim 1 , wherein enabling the phase lock loop in the first mode includes setting an enable signal of a differentiator to a first state and enabling the phase lock loop in the second mode includes setting the enable signal of the differentiator to a second state. 
     
     
         3 . The method of  claim 2 , wherein enabling the phase lock loop in the first mode includes setting the enable signal of the differentiator module to zero such that a differentiator module is not enabled. 
     
     
         4 . The method of  claim 2 , wherein enabling the phase lock loop in the second mode includes setting the enable signal of the differentiator module to logical high such that a differentiator module is enabled. 
     
     
         5 . The method of  claim 2 , wherein setting the enable signal to the first state causes a flip-flop of the differentiator to set to a hold state. 
     
     
         6 . The method of  claim 2 , wherein setting the enable signal to the second state causes a flip-flop of the differentiator to provide an output signal. 
     
     
         7 . The method as recited in  claim 1 , further comprising compensating for a feedback signal comprising a harmonic with the same frequency of an output signal of the phase lock loop, the feedback signal generated by the power amplifier. 
     
     
         8 . The method as recited in  claim 1 , further comprising switching between the first mode and the second mode of the phase lock loop without generating additional disturbances within the phase lock loop. 
     
     
         9 . A system comprising:
 a transceiver module; and   a phase lock loop associated with the transceiver module, the phase lock loop to operate in a first mode when the transceiver module is in a first state and to operate in a second mode when the transceiver module is in a second state.   
     
     
         10 . The system according to  claim 9 , further comprising a power amplifier associated with the transceiver module, the power amplifier determining the first and second states. 
     
     
         11 . The system according to  claim 10 , wherein the first state is to occur when the power amplifier is in a substantially constant state and the second state is to occur when the power amplifier is ramping. 
     
     
         12 . The system according to  claim 9 , further comprising a differentiator to enable the phase lock loop to operate in the first and second modes. 
     
     
         13 . The system according to  claim 12 , wherein the differentiator is to receive an enable signal in a first state to enable the phase lock loop to operate in the first mode and the differentiator is to receive the enable signal in a second state to enable the phase lock loop to operate in the second mode. 
     
     
         14 . The system according to  claim 12 , wherein the differentiator includes a flip-flop, the flip-flop to receive an enable signal in a first state to enable the phase lock loop to operate in the first mode. 
     
     
         15 . The system according to  claim 14 , wherein the flip-flop is to receive the enable signal in a second state to enable the phase lock loop to operate in the second mode.