Filter circuit and communication semiconductor device using the same

Abstract

The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively.

1 - 6 . (canceled) 
     
     
         7 . A semiconductor device, comprising:
 an amplifier circuit for amplifying an analog signal; and   a filter circuit for filtering said analog signal, wherein   the filter circuit comprises   a voltage/current conversion circuit for converting said analog signal from voltage to current, and   a capacitor array which executes signal processing by charging or discharging said current converted by said voltage/current conversion circuit to/from plural capacitors,   said capacitor array is so constructed that said plural capacitors are divided to plural stages to accumulate signals averaged by a capacitor on a preceding stage in a capacitor on a next stage successively.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein said capacitor array comprises: a first switching element for controlling the charge or discharge of each of said capacitors; a second switching element for resetting each of said capacitors; and a third switching element for averaging each of said capacitor on each stage. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein said capacitor array is so constructed that at a timing when said third switching element on a preceding stage is opened, said first switching element of said capacitor on a next stage is opened and before the timing, said second switching element of said capacitor on the next stage resets said capacitor on the next stage.