Semiconductor device

Abstract

A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.

1 - 19 . (canceled) 
     
     
         20 . A semiconductor device, comprising:
 first and second bit line select switch arrays each having a plurality of bit line select switches; and   a sub-memory cell array adjacently disposed between the first and second bit line select switch arrays and having a plurality of local bit lines, a plurality of word lines, and a plurality of memory cells disposed at intersections of the plurality of word lines and the plurality of local bit lines,   wherein the local bit lines are connected to a global bit line through the first and second bit line select switch arrays, and current is caused to flow through the first and second bit line select switch arrays in the same direction at the time of writing,   wherein the memory cell is constituted of a select element and a resistance change element,   wherein one terminal of the resistance change element is connected to a plate electrode shared by other memory cells and another terminal thereof is connected to the select element, and   wherein a potential of the plate electrode is set to a potential between a ground voltage and a memory cell writing voltage.