Apparatus and methods for tuning a memory interface

Abstract

The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

1 . An integrated circuit comprising:
 programmable logic configured to generate one or more bursts to access a memory device;   generate controlled programming information to change parameters of a memory interface responsive to mismatch information;   issuing the controlled programming information to the memory interface;   based on the controlled programming information, automatically tuning the memory interface by automatically adjusting a delay of at least one physical connection of the memory interface by automatically updating a signal strength level of the at least one physical connection wherein the automatically tuning cycles through a plurality of write and/or read data and strobe delay settings until no data mismatches are determined.   
     
     
         2 . The integrated circuit as defined in  claim 1 , further comprising:
 a pre-programmable data register configured to receive programming of the plurality of stored data patterns.   
     
     
         3 . The integrated circuit as defined in  claim 1 , wherein the programmable logic further includes a programmable address generator configured to generate at least one of a read and write address to the at least one memory device. 
     
     
         4 . The integrated circuit as defined in  claim 1 , wherein the logic is further configured to execute a looping routine where the programmable logic continuously reads data patterns between predefined starting and ending memory addresses. 
     
     
         5 . The integrated circuit as defined in  claim 4 , wherein the logic is further configured to determine an expected read data pattern sequence and compares the read data pattern sequence with the expected read data pattern sequence and determines whether a data mismatch has occurred based on the comparison. 
     
     
         6 . The integrated circuit as defined in  claim 3 , wherein the programmable logic further includes a mismatch information generator configured to determine mismatches between data written to the at least one memory and data received from the at least one memory during the looping routine and issue a signal indicating failure of the memory interface when a mismatch is determined. 
     
     
         7 . The integrated circuit as defined in  claim 6 , further comprising a signaling device responsive to the signal indicating failure of the memory interface. 
     
     
         8 . A method for testing a memory comprising:
 generating one or more bursts to access a memory device;   generating controlled programming information to change parameters of a memory interface responsive to mismatch information;   issuing the controlled programming information to the memory interface;   based on the controlled programming information, automatically tuning the memory interface by automatically adjusting a delay of at least one physical connection of the memory interface by automatically updating a signal strength level of the at least one physical connection wherein the automatically tuning cycles through a plurality of write and/or read data and strobe delay settings until no data mismatches are determined.   
     
     
         9 . The method of  claim 8 , further comprising:
 programming the plurality of stored data patterns.   
     
     
         10 . The method of  claim 8 , comprising executing a looping routine to continuously read data patterns between predefined starting and ending memory addresses. 
     
     
         11 . The method of  claim 10 , comprising determining an expected read data pattern sequence and comparing the read data pattern sequence with the expected read data pattern sequence and determining whether a data mismatch has occurred based on the comparison. 
     
     
         12 . The method of  claim 8 , comprising determining mismatches between data written to the at least one memory and data received from the at least one memory during the looping routine and issuing a signal indicating failure of the memory interface when a mismatch is determined.