Wiring board and method for manufacturing the same

Abstract

A wiring board 10 comprises a wiring board main body 21 having a dielectric layer 25 that is the first dielectric layer, an electronic component attaching pad 24 having a connection surface 24 A with which an electronic component 11 is connected, and disposed inside the dielectric layer 25 , a dielectric layer 31 that is the second dielectric layer laminated on the dielectric layer 25 , and the via holes 27 and 33 and a wiring pattern 28 provided on the dielectric layers 25 and 31 and electrically connected with the electronic component attaching pad 24 , wherein a warp reduction member 22 for reducing a warp of the wiring board main body 21 is disposed inside the dielectric layer 25.

1 - 10 . (canceled) 
     
     
         11 . A method of manufacturing a wiring board, comprising:
 (a) forming a pad on which an electronic component is to be mounted and a warp reduction member for reducing a warp of the wiring board on a carrier;   (b) forming a dielectric layer on the carrier such that the pad and the warp reduction member are covered by the dielectric layer;   (c) forming a wring layer on the dielectric layer such that the wiring layer is connected to the pad; and   (d) removing the carrier.   
     
     
         12 . The method of  claim 11 , wherein surfaces of the pad and the warp reduction member are exposed after step (d). 
     
     
         13 . The method of  claim 11 , wherein side surfaces of the pad and the warp reduction member are covered by the dielectric layer in step (b). 
     
     
         14 . The method of  claim 11 , further comprising:
 (e) forming a multilayer wiring layer comprising a plurality of wiring layers and dielectric layers on the wiring layer; and   (f) forming a pad on the multilayer wiring layer.   
     
     
         15 . The method of  claim 11 , wherein step (a) comprises forming the pad and the warp reduction member on the carrier by electrolytic plating using the carrier as a power feeding layer. 
     
     
         16 . The method of  claim 11 , further comprising:
 (e) forming a via hole through the dielectric layer to expose the pad,   wherein step (c) comprises forming a via in the via hole such that the via is connected to the pad while forming a wiring pattern on the dielectric layer.   
     
     
         17 . The method of  claim 11 , wherein a connection surface of the pad is almost flush with one surface of the dielectric layer. 
     
     
         18 . The method of  claim 17 , wherein
 the warp reduction member is disposed on the same plane as the pad,   the thickness of the warp reduction member is almost equal to the thickness of the pad, and   the material of the warp reduction member is substantially the same as the material of the pad.   
     
     
         19 . The method of  claim 11 , wherein the warp reduction member is a metal film. 
     
     
         20 . The method of  claim 11 , wherein
 the warp reduction member is disposed on the dielectric layer located outside a part corresponding to a formation area of the pad, and   the warp reduction member has a frame shape in plan view.   
     
     
         21 . The method of  claim 11 , wherein
 the warp reduction member has a plurality of warp reduction portions, and   the plurality of warp reduction portions are spaced from each other.   
     
     
         22 . The method of  claim 11 , further comprising:
 (e) forming a solder resist layer exposing a connection surface of the pad, and covering a surface of the warp reduction member located on the side of the connection surface of the pad on a surface of the dielectric layer.