US2012099371A1PendingUtilityA1

Method of operating a phase-change memory device

39
Assignee: KIM CHEOL-KYUPriority: Nov 29, 2007Filed: Jan 4, 2012Published: Apr 26, 2012
Est. expiryNov 29, 2027(~1.4 yrs left)· nominal 20-yr term from priority
G11C 13/0004G11C 11/5678G11C 13/02
39
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.

Claims

exact text as granted — not AI-modified
1 . A method of programming a memory device having a resistance-change layer, a first electrode contact layer, and a unit applying a voltage to the resistance-change layer, the programming method comprising:
 applying a reset voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a resistance-change is initiated at a surface of the resistance-change layer contacting the first electrode contact layer,   wherein the reset voltage includes at least two pulse voltages.   
     
     
         2 . The method of  claim 1 , wherein the at least two pulse voltages are sequentially applied. 
     
     
         3 . The method of  claim 1 , wherein the at least two pulse voltages are continuously applied. 
     
     
         4 . The method of  claim 1 , wherein the at least two pulse voltages are applied with a time interval therebetween. 
     
     
         5 . The method of  claim 1 , wherein the at least two pulse voltages are applied with identical magnitude. 
     
     
         6 . The method of  claim 1 , wherein a pulse width of the at least two pulse voltages are equal. 
     
     
         7 . The method of  claim 1 , further comprising:
 applying a set voltage to the resistance-change layer,   wherein the set voltage includes one pulse voltage.   
     
     
         8 . A method of programming a memory device having a resistance-change layer, a first electrode contact layer, and a unit applying a voltage to the resistance-change layer, the programming method comprising:
 applying a reset voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a resistance-change is initiated at a surface of the resistance-change layer contacting the first electrode contact layer, wherein the reset voltage includes at least two pulse voltages; and   applying a set voltage to the resistance-change layer.   
     
     
         9 . The method of  claim 8 , wherein the reset voltage is applied for an equal or shorter amount of time than the set voltage. 
     
     
         10 . The method of  claim 8 , wherein the set voltage includes one pulse voltage. 
     
     
         11 . The method of  claim 8 , wherein the applying a reset voltage to the resistance-change layer includes,
 applying a first pulse voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a first resistance-change is initiated at a first surface of the resistance-change layer contacting the first electrode contact layer; and   applying a second pulse voltage to the resistance-change layer via the first electrode contact layer in the programming step for data writing such that a second resistance-change is initiated at a second surface of the resistance-change layer contacting the first electrode contact layer, wherein the second surface is disposed adjacent to the first surface.   
     
     
         12 . The method of  claim 8 , wherein the at least two pulse voltages are sequentially applied in a same programming step. 
     
     
         13 . The method of  claim 8 , wherein the at least two pulse voltages are continuously applied in a same programming step. 
     
     
         14 . The method of  claim 8 , wherein the at least two pulse voltages are applied with a time interval therebetween in a same programming step. 
     
     
         15 . The method of  claim 8 , wherein the at least two pulse voltages are applied with identical magnitude. 
     
     
         16 . The method of  claim 8 , wherein a pulse width of the at least two pulse voltages are equal.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.