Three dimensional stacked nonvolatile semiconductor memory

Abstract

In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit.

1 . A nonvolatile semiconductor memory comprising:
 a memory cell array included a first and second block;   a first driver disposed adjacent to the memory cell array;   wherein the first block has a first cell unit including a memory cell to be read and a second cell units without a memory cell to be read, and the first cell unit and the second cell units are connected to the bit line,   wherein a word line electrically connected to a memory cell in the first cell unit is connected to a corresponding memory cell in the second cell unit,   wherein a read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the memory cell to be read in the first cell unit, and   wherein the read potential and the transfer potential are not applied to the word line in the second block in the read.   
     
     
         2 . The memory according to  claim 1 , wherein the ground potential is transferred from the bit line to a channel of a memory cell existing nearer to the bit line side than a memory cell, to which the read potential is applied, in the second cell unit. 
     
     
         3 . The memory according to  claim 1 , wherein a timing at which the read potential or the transfer potential is applied to the word line in the first block is before a timing at which all the memory cells in the second cell unit are cut off from the bit line. 
     
     
         4 . The memory according to  claim 1 , wherein a timing at which the precharge potential is applied to the bit line is the same as or after a timing at which all the memory cells in the second cell unit are cut off from the bit line. 
     
     
         5 . The memory according to  claim 1 , wherein even after the read potential or the transfer potential is applied to the word line in the first block, a channel of a memory cell existing nearer to the bit line side than a memory cell, to which the read potential is applied, in the second cell unit is kept to the ground potential. 
     
     
         6 . The memory according to  claim 1 , wherein the memory cell comprises a NAND cell unit.