Single chip semiconductor coating structure and manufacturing method thereof

Abstract

A manufacturing method of a single chip semiconductor coating structure includes following steps. Step 1 is providing a single chip semiconductor which has a plurality of surfaces, and two opposite surfaces selected from the plurality of surfaces are manufacturing surfaces and have a conductive area with a pad thereon, respectively. Step 2 is providing a tool to cover one of the conductive areas with the pad. Step 3 is providing a coating step to form an insulating layer on the single chip semiconductor. Step 4 is providing a removing step to remove the insulating layer for exposing the covered conductive area and the pad. Step 5 is forming two electrodes and each of the two electrodes covers the conductive area with the pad.

1 . A manufacturing method of a single chip semiconductor coating structure, comprising steps of:
 providing a single chip semiconductor, wherein the single chip semiconductor has a plurality of surfaces, two opposite surfaces selected from the plurality of surfaces are manufacturing surfaces and have a conductive area with a pad thereon, respectively;   providing a tool to cover one of the conductive areas with the pad;   providing a coating step to form an insulating layer on the single chip semiconductor;   providing a removing step to remove the insulating layer for exposing the covered conductive area and the pad; and   forming two electrodes, wherein each of the two electrodes covers the conductive area with the pad.   
     
     
         2 . The manufacturing method according to  claim 1 , wherein the single chip semiconductor with the tool is disposed in a film-coater in the coating step. 
     
     
         3 . The manufacturing method according to  claim 1 , wherein the tool is released from the single chip semiconductor after the coating step. 
     
     
         4 . The manufacturing method according to  claim 1 , further comprising a step of forming a connecting layer, wherein the connecting layer covers the two electrodes. 
     
     
         5 . The manufacturing method according to  claim 4 , wherein the connecting layer is formed by an electroplating method and two ends of the connecting layer extend on the insulating layer. 
     
     
         6 . The manufacturing method according to  claim 1 , wherein each of the two electrodes has two ends thereof and the two ends extend on the insulating layer in the step of forming two electrodes. 
     
     
         7 . The manufacturing method according to  claim 1 , wherein positions of the pads are misaligned to each other. 
     
     
         8 . The manufacturing method according to  claim 7 , wherein each pad is disposed on an edge of the corresponding surface. 
     
     
         9 . The manufacturing method according to  claim 1 , wherein a dimension of the single chip semiconductor is 0.6 mm×0.3 mm×0.5 mm or 1.0 mm×0.5 mm×0.5 mm or 1.6 mm×0.8 mm×0.5 mm. 
     
     
         10 . The manufacturing method according to  claim 1 , wherein the manufacturing surfaces are manufactured by photolithography, thin film deposition, etching or doping methods.