Security of Program Executables and Microprocessors Based on Compiler-Architecture Interaction

Abstract

A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings. A method wherein a control instruction encoded with an instruction set encoding contains information about decoding of an instruction that is encoded with another instruction set encoding scheme. A method wherein instruction set encodings are randomly generated at compile time. A processor framework wherein an instruction is decoded during execution with the help of information provided by a previously decoded control instruction.

1 . A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings. 
     
     
         2 . The method of  claim 1  wherein:
 a control instruction encoded with an instruction set encoding contains information about decoding of a second instruction; 
 the second instruction is encoded with a different instruction set encoding from the control instruction. 
 
     
     
         3 . The method of  claim 2 , wherein instruction set encodings are randomly generated at compile time. 
     
     
         4 . The method of  claim 2 , further comprising of:
 adding at compile time to an executable information enabling decoding of an instruction;   the information is added in an encrypted format.   
     
     
         5 . The method of  claim 2 , wherein a constant field within an instruction is scrambled at compile time. 
     
     
         6 . The method of  claim 2 , wherein instructions are scrambled with additional random keys associated with logical program addresses. 
     
     
         7 . A processor framework wherein:
 instructions are encoded in plural instruction set architectures;   an instruction is decoded during execution with the help of information provided by a previously decoded instruction.   
     
     
         8 . The processor framework of method  2 , wherein a control instruction is extracted at runtime before entering the processor pipeline. 
     
     
         9 . The method of processor framework  7  wherein instructions are decoded to a reference instruction set before entering the decode stage of the processor. 
     
     
         10 . The method of  claim 2 , wherein control instructions are implemented as co-processor instructions. 
     
     
         11 . The method of  claim 1 , comprising of:
 analyzing a program executable at compile time;   changing the instruction set architecture encoding of an instruction;   scrambling constant fields in an instruction;   adding information about the instruction set encoding of an instruction into another instruction;   generating a program executable with plural instruction set encodings;   
     
     
         12 . A method, for use in a processor context, wherein:
 instructions in a program executable are scrambled;   a control instruction scrambled with a key contains information about decoding of an instruction that is scrambled with another key.