Scalable Prediction Failure Analysis For Memory Used In Modern Computers

Abstract

One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.

1 . A method for scalable predictive failure analysis, the method comprising:
 gathering memory information for memory on a user computer system having at least one processor;   selecting one or more memory-related parameters;   calculating, based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information; and   setting, based on the calculating, the single bit error value for the user computer system.   
     
     
         2 . The method of  claim 1 , further comprising detecting, subsequent to the setting, one or more single bit errors for the memory. 
     
     
         3 . The method of  claim 1 , further comprising comparing, subsequent to the setting, a counted number of single bit errors for the memory to the value. 
     
     
         4 . The method of  claim 1 , further comprising alerting, subsequent to the setting, if a counted number of single bit errors for the memory at least equals the single bit error value. 
     
     
         5 . The method of  claim 1 , further comprising returning to sleep, subsequent to the setting, if a counted number of single bit errors for the memory fails to exceed the single bit error value. 
     
     
         6 . The method of  claim 1 , further comprising re-setting, according to the method, the single bit error value for the user computer system upon a memory replacement. 
     
     
         7 . The method of  claim 1 , further comprising reporting the single bit error value and any results from the method on a display associated with the user computer system. 
     
     
         8 . A computer program product for scalable predictive failure analysis:
 a computer readable storage device;   first program instructions to gather memory information for memory on a user computer system having at least one processor;   second program instructions to select one or more memory-related parameters;   third program instructions to calculate based on the gather and the select, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information;   fourth program instructions to set, based on the calculate, the single bit error value for the user computer system; and   wherein the first, second, third, and fourth program instructions are stored on the computer readable storage device.   
     
     
         9 . The computer program product of  claim 8 , further comprising fifth program instructions to detect, subsequent to the set, one or more single bit errors for the memory; and wherein the fifth program instructions are stored on the computer readable storage device. 
     
     
         10 . The computer program product of  claim 8 , further comprising fifth program instructions to compare, subsequent to the set, a counted number of single bit errors for the memory to the value; and wherein the fifth program instructions are stored on the computer readable storage device. 
     
     
         11 . The computer program product of  claim 8 , further comprising fifth program instructions to alert, subsequent to the set, if a counted number of single bit errors for the memory at least equals the single bit error value; and wherein the fifth program instructions are stored on the computer readable storage device. 
     
     
         12 . The computer program product of  claim 8 , further comprising fifth program instructions to return to sleep, subsequent to the set, if a counted number of single bit errors for the memory fails to exceed the single bit error value; and wherein the fifth program instructions are stored on the computer readable storage device. 
     
     
         13 . The computer program product of  claim 8 , further comprising fifth program instructions to re-set, according to the method, the single bit error value for the user computer system upon a memory replacement; and wherein the fifth program instructions are stored on the computer readable storage device. 
     
     
         14 . A system for scalable predictive failure analysis, the system comprising:
 a processor, a computer readable memory and a computer readable storage device;   first program instructions to gather memory information for memory on a user computer system having at least one processor;   second program instructions to select one or more memory-related parameters;   third program instructions to calculate based on the gather and the select, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information;   fourth program instructions to set, based on the calculate, the single bit error value for the user computer system; and   wherein the first, second, third, and fourth program instructions are stored on the computer readable storage device for execution by the processor via the computer readable memory.   
     
     
         15 . The system of  claim 14 , further comprising fifth program instructions to detect, subsequent to the set, one or more single bit errors for the memory; and wherein the fifth program instructions are stored on the computer readable storage device for execution by the processor via the computer readable memory. 
     
     
         16 . The system of  claim 14 , further comprising fifth program instructions to compare, subsequent to the set, a counted number of single bit errors for the memory to the value; and wherein the fifth program instructions are stored on the computer readable storage device for execution by the processor via the computer readable memory. 
     
     
         17 . The system of  claim 14 , further comprising fifth program instructions to alert, subsequent to the set, if a counted number of single bit errors for the memory at least equals the single bit error value; and wherein the fifth program instructions are stored on the computer readable storage device for execution by the processor via the computer readable memory. 
     
     
         18 . The system of  claim 14 , further comprising fifth program instructions to return to sleep, subsequent to the setting, if a counted number of single bit errors for the memory fails to exceed the single bit error value; and wherein the fifth program instructions are stored on the computer readable storage device for execution by the processor via the computer readable memory. 
     
     
         19 . The system of  claim 14 , further comprising fifth program instructions to re-set, according to the method, the single bit error value for the user computer system upon a memory replacement; and wherein the fifth program instructions are stored on the computer readable storage device for execution by the processor via the computer readable memory. 
     
     
         20 . The system of  claim 14 , further comprising fifth program instructions to report the single bit error value and any results from the method on a display associated with the user computer system; and wherein the fifth program instructions are stored on the computer readable storage device.